ISE 5.1/5.2 Error

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I wrote a program in vhdl with ISE 5.1 and when I try to simulate the post
translate VHDL model or Post Map or Post place and route, I receive the
follow error:

ERROR: Hidden remap failed
Reason:

None appears in Reason !!!

What is the cause of this error ?
And the remedy ?

I've tried also to upgrade to ISE5.2 sp.3 but the problem remains same.

The program in the FPGA works well but I have ever the dubt that something
inside it is wrong !!!

Regards
Giuseppe



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