ISE 10.0 finally with multi-threading and SV support ?

That is one of the comon EDA questions: What are the benefits vs. the caveats of high level decisions compare to an algorithm working on a global detailed design description.. Early partitioning costs some optimization potential and requires guestimates at the boundaries, but frees up computational ressources that can used to obtain better results within the partitions in the same tool run time. What is better is not easy to say beforehand.

While currently not at the top of the crowd, partitioning based placers still perform pretty well. They were introduced without parallization in mind so partitioning isn't all bad. Another example of this type of tradeoff (albeit no related to parallel algorithms) are all approaches that use clustering. They lose detail to make the overall problem more manageable.

I do not know about Altera, but Xilinx has to do partial partitioning anyway to place flip-flops connected to regional clocks. (well, actually this is floorplanning not partitioning, but it has similar effects on the placement)

Kolja Sulimma

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Kolja Sulimma
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Oh, let's see:

a) When you include an EDK project (.xmp) in your ISE project, the tools should be smart enough to know that the external ports in your .mhs file should NOT synthesize to include I/O pads.

b) The magic line in the .xmp file that makes what I describe in a) actually work should be DOCUMENTED.

c) The ISE project file should be PLAIN TEXT, not some magic binary file that grows and grows. Xilinx, do you know anything about source- code control? I didn't think so.

d) The required directory hierarchy for the EDK is inflexible and very unfriendly for those who use source-code control.

I'm sure I'll come up with more later ...

-a

Reply to
Andy Peters

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