ISA vs. patent/trademark

Hi,

Are ISA covered by patents or trademarks? Is it allowed to develop a processor core for a popular ISA as long as no reference is made to any of the original company trademarks? Many thanks for your comments.

Eric

Reply to
Eric DELAGE
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"Eric DELAGE" schrieb im Newsbeitrag news:4252c3dc$0$3114$ snipped-for-privacy@news.wanadoo.fr...

It all depends what you are up to and against whom, some companies are very quick to get their lawers involved.

However I think it is not actually possible to fully copyright an ISA, because

1) languages can not be patented, any one can learn another language if he pleases so. That is covered by basic human rights I hope. 2) an ISA can be considered a description of some formal language, in any case you yourself can learn to understand the bytecode, etc.. that cant be prohibied. 3) You can buy a smart-dog and teach that dog that ISA (if you are able too), its isnt prohibited to try. 4) You can buy and FPGA and teach that FPGA to understand what you learned in step[2] - that again can not be directly forbidden.

Now, that doesnt mean the lawers want come after you, they can try at least. But by being VERY VERY Careful it is possible to make the case a 'no case' for the lawers. But you really have to have a 'clean implementation' - and you have to withstand any pressure from the lawers who try to prove the opposite.

ARM shuts down, nnARM was forced underground/dead, picoturbo was closed down MIPS shoots as well SPARC is Open for anyone to implement. that the reason why Gaisler did choose SPARC for their space stuff Altera tolerates the GPL version of NIOS-I, but is also trying to shut down OpenSource NIOS-II Xilinx has said they have nothing against 3rd MicroBlaze implementations

my 2cents Antti

Reply to
Antti Lukats

any

Depends on the ISA. ARM, for instance, is covered by thick IP protection layers, and is vigorously defended. 8051, not so much :)

Reply to
larwe

W/ ARM for instance, I understand that they can protect their IP implementation w/ patents or copyrights but what would be the lawwhich prevent someone from implementing a processor core running an ARMv5?

If someone implements a core able to run any compiled w/ gcc using some of the x86 flags, could INTEL prevent him from distributing the core. No mention is directly done of the INTEL name; no claim would be done for any INTEL compatibility of the processor core. What could happen?

Eric

Reply to
Eric DELAGE

The keypoint, I think, is: are we talking about 1) patents (but the ARM ISA is full of instructions developped before it appears) 2) trademarks (but as long as no mention/no claim regarding the original names are done, would it be ok?) 3) copyright (but if an ISA is a language, an someone copyright it?)

Eric

Reply to
Eric DELAGE

lawwhich

Patents relating to specific instruction set features. I don't know what patents they hold specifically; I'm sure there are some.

some

No

for

You could be sued for distributing a product in violation of another party's intellectual property rights. For example, suppose Intel has patents on some aspect of MMX. You implement MMX compatible instructions in an infringing way. They have a claim against your product.

Example: I make a device that plays video off optical disks. It just so happens by accident that my design is exactly the same as, and in fact compatible with, the DVD standard. The DVD consortium can sue me for infringement. They could still sue me with equal success if I can PROVE that I developed my device totally without any reference to their designs.

Reply to
larwe

Point 1: As for MIPS, the unaligned load/store instructions (i think) are covered by patents. In order to implement these, you must obtain a license from MIPS technologies.

Point 2: For trademark reasons you cannot call a processor for MIPS compatible or compliant, without implementing the full ISA. Goto point 1.

(Infinite loop exception, program aborted).

That hasn't stopped people from implementing processors with the MIPS ISA, *except* for the patented instructions. But the people doing this are very careful about not calling the processor for anything related to MIPS...

Kai

--
Kai Harrekilde-Petersen
Reply to
Kai Harrekilde-Petersen

You protect an ISA by patenting some special thing which is required to implement the ISA. I happen to think that the ARM Thumb patent is a load of rubbish.

The basis of the patent is the "ARM Ltd discovery" that less code is better than more code. Code compression for RISC is mentioned already in the original RISC paper by Katevenis.

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Best Regards
Ulf Samuelsson
Reply to
Ulf Samuelsson

See also the ST7 family from ST, and the Motorola HC05 series.....

I heard that the NIOS II is 'very similar' to MIPS - can anyone who knows both cores in detail comment ?

-jg

Reply to
Jim Granville

Q If some processor that is not any way MIPs like can otherwise perform a register ld/st for a word on any byte boundary is that a problem, or only if the rest of it is MIPs like too.

If a processor has a general move n bytes ie mv rd,rs,4 and works on any boundary and any length into memory locations that are also a register, a problem?.

Am I not mistaken that most all cpus allowed unaligned ld/st till the RISC religion took over. Guess I will have to look at the patent.

johnjakson at usa dot com

Reply to
JJ

Trademarks cover only product *names*.

ISA names can indeed be trademarked, hower that would not prevent anyone from copying/using the architecture.

It would only prevent them from selling/promoting/advertising it under the same name as the original.

dk

Reply to
Dan Koren

Are you sure? A lot of the layers appear to be camoflage and not actual protection. The ARM business case appears to be: 1) milk money from people who buy ARM IP 2) if you see somebody else making ARMs, sue 3) try to get an out of court settlement at all costs 4) including by paying the "offender" lots of cash to go away, stop making ARMs and being quiet about the whole business

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	Sander

+++ Out of cheese error +++
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Sander Vesik

"JJ" skrev i meddelandet news: snipped-for-privacy@g14g2000cwa.googlegroups.com...

The Series 32000 definitely had that capability and that was available already in 1982. This was a microcoded machine, but I do not know if the unaligned functions was implemented in microcode. All machines had 32 bit datapaths and registers, and the NS32032 had a 32 bit bus already in 1985. Dont know the background of the invention.

In 1985 there was It is very hard to invent new things

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Best Regards
Ulf Samuelsson                ulf@atmel.com
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Reply to
Ulf Samuelsson

There is a case of this years ago: The Zilog Z80 used the Intel 8080/8085 instruction set and extended it, but used different mnemonics for nearly all instructions.

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Tauno Voipio
tauno voipio (at) iki fi'
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Reply to
Tauno Voipio

I don't know the MIPS in detail (long ago, I read a book on the R2000/R3000 architecture which I picked up in a second-hand bookshop), but there are certainly some fundamental similarities. Each is a 32-bit RISC core, with 32x32-bit registers, orthogonal instruction set, etc. The NIOS II is a little odd (IMHO) in that it has some registers with dedicated purposes and supervisor-only access. I think, however, that quite a lot of 32-bit RISC architectures (ARM, Microblaize) would be "very similar" at this level.

The Nios I was a very different beast, and used sliding register windows in the manner of Sparc. Perhaps the comment you heard was more on the lines of "The NIOS II, unlike the original NIOS, is more of a standard RISC core, such as MIPS" ?

mvh.,

David

Reply to
David

Original RISC paper by Katevenis? While I was able to find a 1983 paper by him, near as I can tell the original RISC paper is still the one by Patterson amd Ditzel in 1980.

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Joseph J. Pfeiffer, Jr., Ph.D.       Phone -- (505) 646-1605
Department of Computer Science       FAX   -- (505) 646-1002
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Reply to
Joe Pfeiffer

It's (NIOS II) a 32-bit, 32 register RISC, but.. Different exception mechanism, different way of doing multiplies (no special registers), smaller instruction set, no branch delay slots, no unaligned load/stores, no fpu, no load-locked/store-conditional, no coprocessors, no 16-bit isa. So not really.

Cheers, Jon

Reply to
Jon Beniston

In article , Joe Pfeiffer writes: |> "Ulf Samuelsson" writes: |> > |> > The basis of the patent is the "ARM Ltd discovery" that less code is better |> > than more code. |> > Code compression for RISC is mentioned already in the original RISC paper by |> > Katevenis. |> |> Original RISC paper by Katevenis? While I was able to find a 1983 |> paper by him, near as I can tell the original RISC paper is still the |> one by Patterson amd Ditzel in 1980.

There were papers containing much of the technical content in the

1960s.

Regards, Nick Maclaren.

Reply to
Nick Maclaren
+--------------- | I happen to think that the ARM Thumb patent is a load of rubbish. +---------------

Yup. See my previous posting about the LINC/LINC-8/PDP-12 machines...

-Rob

----- Rob Warnock

627 26th Avenue San Mateo, CA 94403 (650)572-2607
Reply to
Rob Warnock

better

by

Of course. But the one that tied it all together in a single, coherent bundle was Patterson and Ditzel.

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Joseph J. Pfeiffer, Jr., Ph.D.       Phone -- (505) 646-1605
Department of Computer Science       FAX   -- (505) 646-1002
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Reply to
Joe Pfeiffer

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