Hi all
I have implemented a very easy memory with a few registers, where i can store and also read values for and from my ALU:
I have got 2 questions:
1) The conv_integer procedure does not work here, I always get the errormessage: no feasable subprogram entry for conv_integer. Any ideas whats wrong here? 2) Finally this memory should be synthizeable for a Xilinx ML300 board. What do I have to change that this will be alright? Is there a documention available? I wasnt able to find one online, which says me in a detailed way what constructs I can use!Thanks for any useful hints SD
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
entity memory is generic (width : integer := 32); port (clk : in std_ulogic; rst : in std_ulogic; inp : in std_ulogic_vector((2*width-1) downto 0); addr: in std_ulogic_vector(3 downto 0); wr : in std_ulogic; rd : in std_ulogic; outp: out std_ulogic_vector((2*width-1) downto 0) ); end memory;
architecture rtl of memory is
type reg_type is array (0 to 3) of std_ulogic_vector((2*width-1) downto
0); signal reg_file : reg_type;begin
write : process(clk,rst,inp,addr,wr) variable x_int : integer; begin if rst = '1' then reg_file(0) '0'); else if clk'event and clk = '1' then if wr = '1' then reg_file(conv_integer(addr))