Is there any software I can use to transform state machines in VHDL into drawings?

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng

Reply to
Tianxiang Weng
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Questasim has a FSM debugger option that generates a graphical view of your state machine, but it's not always a great view for documentation purposes.

Reply to
kkoorndyk

:

ware to transform the state machines in VHDL into drawings.

o drawings?

ur state machine, but it's not always a great view for documentation purpos es.

What I have been developing is a set of new hardware circuits that have bee n never used. I want to apply for patents with full state machines design d isclosed. For correctness, the state machines block diagrams should be cons istent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.

Weng

Reply to
Tianxiang Weng

You could use

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to draw your state machines, then export to VHDL.

Reply to
Thomas Koenig

ote:

oftware to transform the state machines in VHDL into drawings.

into drawings?

your state machine, but it's not always a great view for documentation pur poses.

been never used. I want to apply for patents with full state machines desi gn disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistency.

Thomas Koenig, I reviewed the website

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it is a wonderf ul product, but I prefer my coding practice: using VHDL and drawing mutuall y to complete a complex state machine. I use Intel Visio to draw state mach ine block diagrams.

When reviewing a state machine design, it is easier to use state machine bl ock diagrams.

Thank you.

Weng

Reply to
Tianxiang Weng

A codebase I look after puts $display statements in the code that print Graphviz code for each state in the state machine. The testbench exercises the code to pass through all the states. When run, you pipe the output into a .dot file and feed that into Graphviz, which will generate a PNG, SVG, PDF of the state transition diagram.

It's a hack, but it works well enough.

Theo

Reply to
Theo

I believe the Sigasi editor has something like that:

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Cheers, Guy.

Reply to
Guy Eschemann

TerosHDL plugin in VSCode has some rudimentary state-machine detection

Reply to
Svenn Are Bjerkem

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