Is there a verilog version of PicoBlaze?

Hi all,

I have downloaded a VHDL version of PicoBlaze. I can synthesize it with other VHDL modules, my I prefer the use of Verilog, so the only way I can use it with them is through EDIF black-box.

Anyway, life could be better if I can use a verilog version of PicoBlaze directly. Does anyone know if it exists?

Thanks in advance, Santiago.

Reply to
sanpab
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  1. No, a Verilog version doesn't exist. (If you write one, let me know!) This is a PITA.
  2. The latest version of picoblaze uses an NGC file rather than EDIF. You should probably upgrade. Also, you should use picoblaze2 if you can; the extra code space helps.
  3. There shouldn't be any problems synthesising with a black box. (I'm doing something similar in my current design.)
  4. There *is* a problem with simulation though: you will need to find a simulator that can do both languages simultaneously. These tend to cost a lot.
  5. Ken Chapman's kcpsm/kcpsm2 assembler uses template files (e.g. ROM_form.vhd) when it writes the RAMB4 or RAMB16 INIT values. The assembler performs a simple textual substitution, so you can change the template so that it writes Verilog instead of VHDL. The filename can't be changed from ROM_form.vhd though.
  6. The assembler doesn't correctly handle source files if they have names longer than 8 characters, or if they are in a directory other than the directory containing the assembler, or if they are not in the current directory. I contacted Xilinx about this and they said that it wouldn't be fixed. :(

Regards, Allan.

Reply to
Allan Herriman

Check the latest version KCPSM3, I don't use Verilog but the assembler have a Verilog rom form.

Walter.

"Allan Herriman" a écrit dans le message de news: snipped-for-privacy@4ax.com...

Reply to
INS122595

The new PicoBlaze User Guide has a short section on using the VHLD PicoBlaze design in a Verilog environment. The Xilinx ISE software includes mixed VHDL/Verilog support. The other option is to instantiate the PicoBlaze design as a black box. Either way, check out page 69 in the following document.

PicoBlaze 8-bit Embedded Microcontroller User Guide for Spartan-3, Virtex-II, and Virtex-II Pro

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Also, as described on page 72, the KCPSM3 assembler generates a Verilog file describing the instruction ROM, which is useful for simulation.

The latest PicoBlaze design is available from the following site.

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--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

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--------------------------------- Spartan-3: Make it Your ASIC

Reply to
Steven K. Knapp

Hi Walter, do you know where I can download KCPSM3? The Xilinx site requires a user name and password, but I can't find a page that will allow me to register (again).

Regards, Allan.

Reply to
Allan Herriman

Allan,

To register and download Picoblaze3:

- Goto

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- Click on 'PicoBlaze for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs'

- Click on the 'Download' button

- Click on 'Create an Account' button

Cheers, Shal> >

Reply to
Shalin Sheth

got it, thanks.

First impressions:

Picoblaze3 has 16 registers vs 32 for Picoblaze2.

Some bugs in kcpsm2.exe are also present in kcpsm3.exe (see webcases #533179 and #533195).

Kcpsm3.exe can't compile code that compiles with kcpsm2.exe. (This violates one of the cardinal rules of EDA - don't break existing designs.) The problem seems to be that kcpsm3 doesn't accept register names of the form 's00', which is the only form that kcpsm2 accepts.

Regards, Allan.

Reply to
Allan Herriman
[snip]

It appears that web case #533195 relates to the DOS 8.3 filename requirements for the KCPSM3 assembler. This is an unfortunate side effect of maintaining compatibility with the widest number of development computers and with the original choice of programming languages to create the KCPSM3 assember.

One alternative is to use the more modern Mediatronix pBlazIDE graphical development environment, which is also no charge. The instruction nmemonics are slightly different than the KCPSM3 assembler but the pBlazIDE software has a code import function that reads KCPSM3 code. Furthermore, the pBlazIDE software includes an instruction-set simulator.

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There are some differences between the PicoBlaze controller for the Spartan-3, Virtex-II, and Virtex-II Pro FPGA families and the older version available for just Virtex-II and Virtex-II Pro. The latest incarnation includes two new instructions (COMPARE, TEST) plus a 64-byte scratchpad RAM, although the number of registers dropped back to 16 from 32.

You can use the NAMEREG assembler directive to handle the different register assignment. Here's an example. Just add the following code to the start of your

NAMEREG s0, s00 ; alias old register name s00 to s0 NAMEREG s1, s01 ; alias old register name s01 to s1 ... NAMEREG sF, s0F ; alias old register name s0F to sF

Then the remainder of your code should compile using the old names. However, you still need to adjust the register assignments for the upper 16 registers.

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs

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--------------------------------- Spartan-3: Make it Your ASIC

Reply to
Steven K. Knapp

That's pretty much the response I expected.

Regards, Allan.

Reply to
Allan Herriman

Dear Steve/Allan: What would be needed in my Picoblaze IDE to support Verilog. Please let me know, so when I find the time I can add that.

Regards, Henk van Kampen

Reply to
Henk van Kampen

Hi Henk, it just needs to be able to generate the file containing the ROM contents in Verilog instead of VHDL. Kcpsm3 generates files in both languages, perhaps you could study what it does.

This doesn't help the OP though, as the core itself is written in VHDL. Steve, would there be any problem if a third party (e.g. me) were to publish a behavioural Verilog description of picoblaze[123]?

Regards, Allan.

Reply to
Allan Herriman

Allan: The Picoblaze cores are, although VHDL, just instantiations of LUTS and FF's. So a straight translation should be possible. Henk

Reply to
Henk van Kampen

Possible, yes, but would it be frowned upon by Xilinx?

Regards, Allan.

Reply to
Allan Herriman

I am not the official word of Xilinx but if you are buying Xilinx devices to use that code in, I doubt you will have a problem with this. If you are trying to re-target this code to another vendor's FPGA, then you might. The code was written to sell Xilinx FPGAs and as long as it does that in either VHDL or Verilog form, then I would not worry to much about the translation. My suggestion however is to just synthesize your design with the processor defined as a black-box in you Verilog code and use the provided NGC file. If you want to run a behavioral Verilog sim using it, then you can translate the NGC file to a structural UNISIM-based model using NGC2HDL. Since it sounds like the original is structural, this should be practically the same thing as the VHDL version. I would not suggest implementing the Verilog file produced by NGC2HDL however as it is only really intended to be used for simulation so I would stick with the original NGC file for implementation to be safe.

-- Brian

Reply to
Brian Philofsky

I haven't used picoblaze, so take my comment accordingly: If picoblaze is placed in the source code using generates, it may not be possible to do it in verilog and retain the placement as well as the parameterization. If using synplify, you can compile the VHDL with the mapped output to verilog turned on to get a structural verilog model that you can use for simulation. Be aware that SRL16's may not be initialized properly though (I don't know if Synplicity fixed that bug in

7.5.1).

Allan Herriman wrote:

message news:...

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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Reply to
Ray Andraka

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