As a sample here is some code. To be clear: I am not looking for alternate ways to code the following always block; I would like to know a way to access the power on reset from verilog. The block is just a simple example of where a reset might be used. I am aware that flip flops in an fpga get initialized globally upon power up.
reg faultReg3; always @ (posedge slow_clk) if (reset) faultReg3
I believe you're looking for a way to poke at the GSR (global set/reset)? You didn't specify a device, but if you look in the library guide (doc/usenglish/books/manuals.pdf in the install dir), there are STARTUP_VIRTEX(|2|4) and STARTUP_SPARTAN(2|3) primitives that allow you to touch the GSR.
Hope that helps.
Have a wire in your top level named "reset" with no source. The synthesis tools should recognize this and replace "reset" with the GSR net. Instantiate the top level in your testbench, and in the testbench, do something like:
assign uut.reset=(gsr_reset);
Your testbench drives gsr_reset, maybe active for 100nS or so.
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