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Is there a means to conditional synthesis in VHDL?

Hi, I am designing a bunch (about 100) of short length tap (5 taps each) FIR. The tap coefficients would be many 1...31. I want to use multiplier adder graph method for the multiplication. That is, multiplying 15 will be implemented as left shift 4 bits, then minus the original. I would like VHDL can intelligently select one of 16 multiplication structure. Is that possible? Or, I have to write C code to generate a VHDL doc? Are there other better methods? Thanks

Reply to
fl
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You *can* do it with VHDL's if...generate construct. But it tends to get pretty clunky, and you may find that a C-based code generator is less painful.

VHDL is a ton better than Verilog for this, because you can freely use functions to manufacture the values of constants (based on other constants). Together with VHDL's wonderful unconstrained array mechanisms, you *should* be able to do what you need. But it won't be trivial, and testing it in all the possible combinations of cases will be a challenge.

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Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

If you're targetting an FPGA that has hardware multipliers, a likely better method is to write your code so that the multiply can be inferred and implemented using the hardware multiplier. It's higher performance, consumes no logic cells and is quicker and easier to write/debug/maintain. Take a look at the recommended coding styles for your intended targetted FPGA.

Kevin Jennings

Reply to
KJ

Just run it through synthesis with the coefficients in as constants.

You'll be surprised (well, I was). When I had a long filter with small coefficients, I had to jump through hoops to get Synplify to use the hard multipliers instead of it being clever and doing shifts and adds!

Cheers, Martin

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martin.j.thompson@trw.com 
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Reply to
Martin Thompson

You can also use a case statement and hope that the compiler does not suck:

case factor is when 0: y

Reply to
Kolja Sulimma

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