I am performing active-module P&R for partial reconfiguration. My fixed logic is 30K (ASIC) gates, and the variable logic modules are 0.5 & 2K gates only...Now I am P&R the variable modules with a blackbox for fixed module, how come it takes over 30 minutes but still ISE 6.1 couldn't finish this small module.
I want to know whether the P&R time is more related to my chip size OR the size of my FPGA(Virtex2, 6000K).
Besides that, how may I derive the output file names in multi-pass P&R, e.g.
It sounds like you have very aggressive timing specs. How fast are you clocking your FPGA? There should be a *.par report file that gives you some details about your design. Does it show your design having many levels of logic?
I've never done ASIC design, but perhaps you folks don't use flip-flops a lot. FFs are "free" in FPGAs so we tend to stick as many of them into our datapaths as we can. I habitually stick in FFs after only a couple levels of logic, if I can afford the latency. Sometimes I'll throw in one right after a single AND gate because it's "free".
By "chip size" do you mean "design size"? I don't think the capacity of your FPGA makes a difference, unless your design is close to 100% utilization, then the tools have less room to work, on top of more routing congestion.
Having too much space might also be a problem if the tools place your logic far apart just because they can. If you see it doing that (by looking with Floorplanner) you might want to set an area constraint to force your logic into a reasonable area..
The speed grade (e.g. -6,-7,...) of your FPGA might be more of an issue than size.
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