Is it possible to save the FPGA state periodically?

Assuming you are not using PLL's - stop the clock

But I need the ability save the state then power off the fpga board and then restore the state at some other time. Thus I need to store the fpga state in flash storage device. I was curious if the JTAG tool that comes with the FPGA software will provide such capability.

Any

As far as I know there no ready to use tools that support this, but newer xilinx part can read out flop-flop state via the configuration port if the design suports this. (Readback Capture)

I am not sure, but I believe that BRAM content can't be read out this way, so you need even more application support, such as making sure that FIFOs are emptied, caches are invalided and other RAMs are read out by the application before powering down.

I guess it can be done without any principal problems but will be very challenging in practice.

Regards,

Kolja Sulimma cronologic

Any

Hi, early Xilinx FPGA Families (X3000) had a power down feature with battery backup. thus the State of the FPGA is saved in itself when powering off the board. Since todays FPGAs are also SRAM based, it might still be possible to to do something like that.

Have a nice synthesis Eilert

Actel Igloo have a pin to freeze operation and maintain state at close to zero power.

Jan Coombs

IIRC, the ram (block and distributed) data are part of the configuration stream. So, if your FPGA logic can store and retrieve its state to block rams, all you have to do is store the state to block ram and read back the configuration. Then use that configuration (instead of the normal one) when you power back up. Naturally, your FPGA has to be able to initialize state from rams, which means the original configuration needs to have the "cold reset" state data for the rams.

Andy

There was a thread on this topic in the Xilinx forums recently. The block RAM readback uses the same ports as your logic. So you can't really do it with a running design. If you have a way to freeze the operation (like de-asserting the global write enable), then presumably you can do this. There are "startup" blocks on most of the newer devices that allow you to muck with the global signals, but you might have other issues, not the least of which is that the global start-up signals have significant skew over the FPGA fabric, so you might also need to gate off your clocks. All in all, I think this would be a pretty ambitious project to get working.

-- Gabor

Excellent points. I took it as granted that a snapshot (to be used for recovery) of a design would necessarily have to be taken while the operational logic was frozen anyway, for the snapshot to have any coherency.

Given that some portions of the FPGA would have to remain working to transfer register contents into rams, use of a global clock/write enable to freeze the design would not be possible. Of course those portions used for the transfer to/from ram at shutdown/startup would have to use conventional initialization mechanisms (reset/preset).

There would likely also be external interfaces, etc. that would need to have special re-initialization behavior to restart communications with external systems that may or may not have experienced the same event.

Andy