Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5

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Hello guys,
I have a system FPGA in vhdl for the virtex board and would like to
generate DDR controller . When i tried to generate a DDR SDRAM
controller using the MIg1.5 it give verilog files.and i wasnt able to
see any settings for the language selection in the mig too.
thanks in advance
subin


Re: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
Hello guys,
I have a system FPGA in vhdl for the virtex board and would like to
generate DDR controller . When i tried to generate a DDR SDRAM
controller using the MIg1.5 it give verilog files.and i wasnt able to
see any settings for the language selection in the mig tool.
thanks in advance
subin


Re: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
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Whne you're running the Core Generator, choose 'Project Options...' from
the Projects menu. This will bring up a dialog box. Choose the
'Generation' tab and in the 'Flow' box choose VHDL. Most of the cores
will give you an option to create or regenetate cores using the new
settings or using the previous setting.

---
Joe Samson
Pixel Velocity

Re: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5
hi,
it's true, but i was not able to run the mig from the core
generator.don't know why.
Actually i am opening the mig from the installed directory(there is a
batch file named mig.) .
subin
Joseph Samson wrote:

Quoted text here. Click to load it


Re: Is it Possible to generate VHDL code for DDR SDRAM using Mig1.5

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Hi subin,

opening this batchfile, you should find something like
     mig -cg_exc_inp test\mig_input.txt -cg_exc_out mig_output.txt

so - edit "test\mig_input.txt" and change
     SET_PREFERENCE designentry verilog
to
    SET_PREFERENCE designentry vhdl

btw: you'll have to change the other entries,too, for changing i.e. the
part etc.

good luck
Jochen


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