Is it possible to define an Integer so it could be incremented and return to 0.

First of all, sorry for my English. What I want is:

variable int : integer range 0 to 64:=0; begin process begin int := int + 1; end process;

And the values: 0 1 2 3 4... 64 0 1 2 3 4 5....

But the real case is that : 0 1 2 3 4 ... 64 64 64 64 64 64 64

My best Regards

Pablo

Reply to
Pablo
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hi Pablo

You want wrap-around at some upper limit.

Really? That seems strange. You should get a runtime error when you try to increment from 64 to 65, because 65 is outside the range of the variable.

You can easily do it...

if int < LIMIT then int := int + 1; else int := 0; end if;

However, if your limit is "all ones" in a binary number (e.g. 31, 63, 127, 255) it may be simpler to use UNSIGNED data instead of integer data. UNSIGNED values are a vector of std_logic bits, and arithmetic will wrap around from (2**N)-1 to 0.

You may get more help on comp.lang.vhdl.

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Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Reply to
Jonathan Bromley

You can easily do it...

if int < LIMIT then int := int + 1; else int := 0; end if;

Shouldn't this be:

if int < LIMIT then int := int + 1; else int := LIMIT ; end if;

BTW, I used something very similar to age items in a queue.

Regards, G.

Reply to
ghelbig

Quite possibly. I understood the OP to mean that he wanted wrap-to-zero behaviour, and was getting something different. Either way makes sense, depending on the application.

Note that you can also get wrap-to-zero behaviour using "mod":

int := (int + 1) mod (LIMIT+1);

but that is unlikely to be synthesisable unless LIMIT+1 is an exact power of 2.

Apologies if I misled anyone.

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Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

G's code: if int < LIMIT then int := int + 1; else int := LIMIT ; end if;

-------

let's see.. initialize int to 0 LIMIT is 3 int < LIMIT ? int Y 1 Y 2 Y 3 N 3 : : N 3

-Dave Pollum

Reply to
Dave Pollum

Thanks to everyone for your advices. It has been very usefull for me.

Pablo

Reply to
Pablo

If the limit were "all ones" (2**N-1, which it is not in this case), then you could just:

int := (int + 1) mod LIMIT+1;

And it will synthesize without additional hardware.

If LIMIT+1 /= 2**N, the the above will still simulate correctly in a test bench, but most synthesis tools will not accept it (rem, mod or divide by non-integral power of two).

Again, this is a rollover, not a saturate behavior.

Andy

Reply to
Andy

Finally I have tried to implement my desing with Mod Operator but all the design seems to fail. This is my code:

if(read = '1' and fifo_empty='0') then addr := (addr - 1)mod(2) end if;

Now I have read in a news group that MOD operator is not synthesizable when:

- A mod B when B is not a power of 2.

- A mod B when both A and B are not constant.

Exactly it says: "a mod b" means "the remainder when a is divided by b. Note that unless 'b' is a power of 2 or both a and b are constants, the mod operation is most likely not synthesizable.

The first sentence is perfect, but the second one involves that the operator has not sense.

Could someone tell me if this is true??

My best regards

Pablo

Reply to
Pablo

Are we supposed to guess what the failure is?

So addr will count from 0 to 1 and back to 0....a toggle flip flop....probably not what you want but that's what your posted code will do. I'll bet the simulator would catch that too, did you simulate?

Generally speaking that's true...that's why if you need a counter that counts from 0 to 17 (or any other non power of 2 modulus) and back to

0, you code it so that if it equals 17 then reset it to 0....but I digress.

Why does it not make sense? I'm assuming that you're confused about the "or both a and b are constants" part of the second sentence (again, take the time to let people know what exactly is your confusion). If A and B are both constants, then A mod B will also be a constant and can be computed by the synthesis tool. Here's another hint, constants do not get synthesized....as logic in terms of gates....they reduce down to things that are always either '1' or '0'...which is used in the logic optomization process.

Kevin Jennings

Reply to
KJ

Thanks kevin, I will try to explain as better as possible. Of course, my English is not perfect.

My real code is this:

if(read='1' and empty='0') then addr := (addr + 1)mod(64); -- So as you said, addr INCREMENTS its value until 64. In this moment it init to 0. That's the use of mod. end if;

My confusion is the following:

Addr is defined as an Integer Variable in the proccess body. Of course is not constant, so its value is increment in each clock cycle. So: Could I use mod in my code??? Could Mod operator be used with variables or signals??

Thanks so much

Reply to
Pablo

Based on the sentence you quote B is 64 in your case and it's a power of two so mod would be synthesizable for you. In any case most of today's synthesizers can give you a divider/mode for more general case but you probably wouldn't want it.

Another solution for your problem could be to declare addr as a 6 bit integer in which case it would wrap from 63 to 0 by itself without the need for mod operator.

Reply to
mk

So as you said,

Yes. It will synthesize just fine because you're trying to get the value of (Addr +1) mod 64 and 64 is a power of 2.

Yes.

Kevin Jennings

Reply to
KJ

A 6 bit integer?????.

Could you tell me how could I define this kind of variable??

Reply to
Pablo

I suppose so, but kevin, I think that Xilinx doesn't synthesizes this. The design fails in the moment that I include the Mod Operator.

Pablo

Reply to
Pablo

Then either

- Don't use Xilinx if it doesn't support computing X mod 64

- Change the code to be of the form shown below

if (addr =3D 63) then addr

Reply to
KJ

What is it doing that you don't like? Are you getting an error message from XST, or is it not simulating the way you think it should, or what?

You should know that 0

Reply to
Andy

Yes Andy, this is ok; 0 to 63. No problem.

The problem is that design fails when I do this operation. Xilinx doesn't get any error message.

Reply to
Pablo

I have already tried to implement this design, but the system fails again. I think this is a delay problem.

Reply to
Pablo

I've asked before and you haven't responded....last time....

- WHAT is the failure?

- Have you simulated the design?

- Does the simulation produce the results you expect?

Kevin Jennings

Reply to
KJ

Thanks but I suppose that I cannot explain the problem as you would like.

Thanks again.

Pablo

Reply to
Pablo

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