Is it possible to debug a vhdl design over jtag?

Hi,

I would like to debug a vhdl design over Jtag. Is it possible?. As XMD for EDK but for vhdl code.

My best regards Pablo

Reply to
Pablo
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yes

Reply to
Antti

check out "ChipScope Pro"

Reply to
comp.arch.fpga

ChipScope is an awesome way to get "eyes" into the operation of the internals of your circuitry. It does not provide the capability to "debug" like software where you can tweak registers, memory, PC, etc on the fly. It has been a savior many times when trying to figure out why something that should have happened, but didn't.

Tricks of the trade with using CS include:

1) Make sure you have MORE than what you want brought out in the triggers. Rebuilding larger systems can take a long time. 2) Make sure you have MORE than what you initially think you need in the data collection. Same reason as above. 3) Basic w/ Edges is a god-send and should be the default setting for data. 4) There is a hard limit on the amount of data/trigger signal you can have per ILA (256, maybe 512). If you need more, you can more ILA's, but its best to try to limit the signals you need to fit into an ILA. If what you need to see won't fit, then maybe you need to re-think exactly what you need. 5) ChipScope can be used together w/ XMD. This can allow you the ability to inject certain conditions without having to run large software programs to probe hardware.
Reply to
morphiend

Synplicty's Verify product merges the capabilities of Xilinx chipscope with a "source level debugger" operating with your vhdl/verilog. "source level debugger" is a generous title, but it is the closest to the real thing available.

Andy

Reply to
Andy

For the purpose of this discussion VHDL is a language describing hardware. Every change in code requires new hardware to be synthesized. For this simple reason software style debugging is not really possible with real hardware. However, you can debug all you want (before going to hardware) with VHDL simulators such as, for example, Modelsim, or Active HDL.

/Mikhail

Reply to
MM

Good point. Some prefer working out the logical problems in a tight loop at the code level on a simulator. This avoids waiting for a special place and route on each try.

-- Mike Treseler

Reply to
Mike Treseler

Thanks for your advices. I suppose that Chipscope is a good option.

Reply to
Pablo

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