IPIF user logic vs. Component insertion

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Hi at all

I tried to insert a Copmonent in my user logic of IPI


COMPONENT asimonh

PORT
clk : IN std_logic;     -- Clock Inpu
rst : IN std_logic;    -- Reset Inpu
asip : IN std_logic;    -- Input from Bu
asim : IN std_logic;       -- Inputvom Bus
dataout : OUT std_logic_vector(31 downto 0); -- Output vecto
enout : OUT std_logic        -- Output signa
        )
END COMPONENT

When I insert a Component in my user logic and map this i get
error

 ERROR:NgdBuild:466 - output pad net 'dataout<0>' has illega

connection.

ok, then i put IBUF to outputs and OBUF to inputs of my component

Then i implement the design with ISE and there were no problems. The
I tried it to implement it with EDK and I get the Errors

ERROR:NgdBuild:455 - logical ne

'myasimon/myasimon/USER_LOGIC_I/dataout<0>' ha
   multiple drivers. The possible drivers causing this are
     pin dataout<0> on bloc
myasimon/myasimon/USER_LOGIC_I/Inst_test with typ
   test
     pin PAD on block myasimon/myasimon/USER_LOGIC_I/dataout<0
with type PA
ERROR:NgdBuild:455 - logical ne
'myasimon/myasimon/USER_LOGIC_I/dataout<1>' ha
   multiple drivers. The possible drivers causing this are
     pin dataout<1> on bloc
myasimon/myasimon/USER_LOGIC_I/Inst_test with typ
   test
     pin PAD on block myasimon/myasimon/USER_LOGIC_I/dataout<1
with type PA

aso


What for a problem can it be


Is interessting, that thus IOs in the Component, wich are insertet i

UCF File are ok


Re: IPIF user logic vs. Component insertion
Hi,
     I dont know if this will help you are not..Did u include ur
component in *.pao file

--
Parag Beeraka


re:IPIF user logic vs. Component insertion
Thank you very much beeraka !!

That was it !!!  :



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