Hello
I use Xilinx ISE 6.1 for synthesis. I discovered in the floorplanner that there are used very much IOB's. Even more than used IO pads. Why that ?? Is it for the reason of timing constraints (for example delays)?? As far as I know, I haven't made any timing constraint in my design. Is it possible not to use so many IOB's. How can I tell ISE to do so ?
Greatings Tobi.
Hint: IOB's are not created by themselves.
IOB's are created by inputs and outputs of the top level module in ISE. Normally you can account for all of the IOB's from the inputs and outputs of the design. The only other possibility is that you have turned on "Use Bonded I/Os" in the place and route options (not default) which allows use of unassigned pads for route through. If you're seeing IOB's used in the floorplanner, you may have some LOC constraints assigning internal logic incorrectly into IOB's.
IOBs can be used as general resource and the tools can make use of these resources. Try the switch "USE BONDED I/OS" in the P&R properties to see if that makes your issue go away.
John Adair Enterpoint Ltd.
This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted.
Thank you for your advice. Ahm, but where is it possible to set the switch? Is it done in the ucf-file or in a GUI ?
Tobias
John Adair wrote:
Look in the GUI. It can probably also be done at command line/batch file too but I don't use command line very often.
It might be worth looking at exactly what is being used in the IOBs with FPGA Editor. You might find you don't have a real issue but of course that depends on your design and your future plans for unused IOBs etc etc.
John Adair Enterpoint Ltd.
This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted.
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