Internal Signals and other questions with ModelSim XE/II Starter 5.7g VHDL Testbench

Hello,

i am trying to learn how to use ModelSim with a VHDL Testbench, but i don't find any answers on a few of my answers. At the moment i start ModelSim always via "Simulate Post-Translate VHDL" from Xilinx Project Navigator.

1) I can see all my stimuli, which are mainly the external in- and outputs. They seems to toggle fine. But how can i display the internal signals ? Is the only solution to assign a port to an internal signal to see it in ModelSim. I already tried to simply define new signals, they are drawn in ModelSim, but it seems they are not connected to the real signals. I think i was able to add internal signals via "Signal" window, but next time i simulate the signal was lost again...

2) I am currently can simulate my design once. When i external edit my vhdl source or testbench i always must close ModelSim and restart it via Xilinx Projects Manager. If i don't close it, i get an error message, that "ModelSim is already running". Is there a more convenient way ?

3) I found a few nice commands like "view wave", "add wave *". Is there a command for full zoom ? Where can i say, that certain commands should be executed e.g. after drawing of a wave ?

4) Every time when i open ModelSim the wave window is only a small window, positioned at right/lower corner of my screen. I already edited the wave window "geometry", saved it to default name modelsim.tcl of my project directory. But on next restart same windows size and position as before. Must i move this file to a certain position. Is there a command like "use preferences" that i can execute like in question 3 ?

5) In my vhdl source file i use a "std_ulogic_vector", because i want to use tristate pins, for bidirectional data transfer of data. In the testbench the xilinx tool created a testbench with "std_logic_vector". It compiles fine. When i change it to "std_ulogic_vector" in testbench, ModelSim brings a compile error, that source and testbench does not fit together. I already use 'Z' for assignments and it seems to work. Should i just ignore this or must i pay attention when doing it this way ? ModelSim can handle tristate logic ?

6) Is there a FAQ for such questions ?

So enough for now,

Martin Maurer

Reply to
Martin Maurer
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Don't know. I size windows manually.

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-- Mike Treseler

Reply to
Mike Treseler

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Under the File menu of the waveform window there are options for saving the current display format, including the signals you have displayed, and then restoring it again later.

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Yes. I find ModelSim to be very convenient and friendly. Define a "project" (read the help text). Add your VHDL files to the project. After you edit one of the files, click on the Project tab. A question mark will appear by the file if has been changed since you last compiled it. Select the file and click the Compile button. At the ModelSim command prompt enter "restart -f". The simulation will be restarted and ModelSim will load the newly compiled versions of any files that have changed.

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Click anywhere in the waveform window and press "f". There are also menu buttons for doing this.

You can put any sequence of commands you want into a "do" file.

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Size the windows the way you want them. Click Tools -> Save Preferences -> Save.

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You should use std_logic_vector, not std_ulogic_vector, for bidirectional buses. You can connect std_logic to std_ulogic, but you can't connect std_logic_vector to std_ulogic_vector without using a conversion function. The ieee.std_logic_1164 package comes with functions for doing these conversions. Look in the package.

Reply to
Charles Bailey

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