Internal pull down on the FPGA.....

Hi all, I am facing a problem with my design. In which i assigned tri state buffers to drive a bus which is connected to sixteen identical blocks. This bus is controlling the register updation. But in the default configuration when all blocks are driving high impedance to the bus the bus is going to '1' state by internal pull up. I want to know is there any way to pull down the internal signals in the Xilinx FPGA (specifically Virtex 4 or Virtex E). regards Sumesh V S

Reply to
vssumesh
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You can put a PULLDOWN directive in the UCF for those pins. Check out the Constraints Guide, I think. Or search for PULLDOWN on the website. There is also a default setting in one of the files if you are using the EDK. I think it has to do with bitgen options. I can't remember exactly where that file is though. Sorry! Alternately, you can put an attribute in your HDL. There are multiple ways to do it.

Good luck.

Reply to
motty

If you're talking about an internal tristate which is emulated - not instantiated - in more recent Xilinx families and all Altera devices, you have two solutions I can think of:

Use logic that looks for no TRI enables in order to drive the tristate low, or Invert your logic so the inputs to all the tristates are inverted and the destination of those tristates is also inverted; the undriven state is still a logic 1 but you're now inverting it at your input.

Reply to
John_H

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