Internal Loading in Spartan3

I am using the EDK to configure a sytem using the MicroBlaze core. We have several user IP's that are used to perform various functions. One of those is a 3-wire serial interface module. It provides several different interfaces to whatever chipset we are talking to (each one uses a different protocol). The data line in this module is used as both input and output. Everything is configured correctly up to the top level.

I have one port that I route up through my verilog into the user logic and out to external pins. This port is used as a debug signal. I can connect internal signals at the lowest level of my code and bring them out externally. This has worked for us in the past with no problem. However, for this particular build of the module, if the debug port is being used and brought out externally, then there appears to be an extra capacitative load presented on the serial data interface line. Writing to our parts is fine, but reading back does NOT work when a scope probe is attached. We found that a 1 to 0 transition in the readback data is actually read in as a 1. Removing the scope probe works fine.

If I take the debug port out completely (not routed externally) then everything is fine. The connections are all still there interanlly, but just not routed to an output port. I can't figure out what the XST tool is doing that is adding extra load to that particular signal. All I am doing is adding a little more logic to the module. The timing analysis is fine. It is actually being clocked 1/3 slower than rated.

I have tried registering the debug output as well and that hasn't worked. Is there a way to tell what is going on here, or does anyone have suggestions?

Like I said, it works, but this behavior scares me. I would like to know EXACTLY what the tools are doing.

thanks

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motty
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