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Internal architecture of lut

Hi all,

I am a beginner in FPGA arch. I was going through the Spartan 2 architecture where I found that each lut can be configured as a 16 bit ram. That means lut is a decoder + a 16 bit register.

This might be a foolish quesiton but please clarify me.

Thanks.

Regards, Mohammed A Khader

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Mohammed khader
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This won't answer your question but here are some sources I have found helpful for better understanding what goes on under the hood.

See if your favorite library can find one of these books Betz et al, Architecture and CAD for Deep-Submicron FPGAs Trimberger, Field-Programmable Gate Array Technology

Then there are journals like IEEE Trans. VLSI, proceedings of the yearly ACM SIGDA Intl. Symp. on FPGAs, device vendor patents, etc.

Jan Gray

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Jan Gray

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