intermitent boot in V4

Howdy Clark,

I didn't go over your bitgen options, but are you using the DONE to let you know when to stop sending CCLK's? Numerous people (including myself) have been bit by the "ALMOST DONE" pin:

In select-map mode, when DONE goes high, it really means "not quite done yet" or "you're almost done". By default, CCLK has to be strobed several more times after DONE goes high.

Whatever your solution, be sure to post it here.

Good luck,

Marc

We had a similar issue with a V2 pro system last year and the issue was related to timing, the DONE light would always signal completion, but the memory test built into the BRAM to run on the PPC would fail. The part that was spec'd to be on the board was a -6 but the item was changed on the BOM to a -5 (b/c of availability) and no one told the firmware / software team, so we were meeting all timing according to XPS / ISE, but that was for the wrong part. You might want to verify that everything has been specified correctly for the system you are targeting.

Greg

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Don't think this is it because (a) this had been booting fine for several months on the same hardware (b) I'm already using the slowest speed grade (-10)

but thanks for the lead. -Clark

With the PPC in the Virtex-IIPro, the advice is to _pulse_ the Prog pin at the appropriate time (Impact does this for me) - that was after JTAG config. I can't recall hearing a satisfactory explanation why; but it DID give an utterly reliable boot after a 10-20% success rate previously.

Perhaps the same is true of the PPC in the V4? Searching Xilinx support for "pulse PROG pin" may yield more info

- Brian