Hi,
I need to interface 2 ADCs and 1 DAC to a Spartan-II FPGA running at
57.6MHz. My data (12-bits wide) needs to be sampled at 200kHz and to save pins I'm going to be using serial ADCs/DACs.As I understand it, using the SPI protocol I would need to read/write
16-bit words at 200kHz needing 3.2Msps converters. From what I've read about SPI, all slave devices connected to the same master have to share the same I/O bus and have separate CS pins.- What I can't understand is, if I need my 2 ADCs and 1 DAC to communicate with the FPGA simultaneously, how do I achieve this when they have to share the same bus?
- Are there application notes I could refer to for guidance (I haven't been able to locate any by googling)?
- Would I need separate serial clocks (SCLK) for each converter and can I generate the SCLK using counters, so for instance to get a 3.2MHz SCLK period, count 18 clock cyles in the 57.6MHz domain of the FPGA system clock?
-Do I have to feed SCLK into a clock output pin or a will a general I/O pin do?
thanks, Mees