Hi,
It's not the first time this question has been asked, but I'd like to know todays state of art: Are their any devices at Altera, Xilinx or others, capabable of handling the fast throughput of high-speed ADCs (1 GS), such as Atmel's AT84AD001B or NS ADC08D1000 ? Preferably without an external DMUX-device... Using the ADC's internal DEMUX leaves us with 16 500 MHz LVDS lines per channel.
Thanks,
Alex
500Mbps per LVDS pair doesn't sound too fast. I'd be interested in knowing whether there are any recent FPGAs that *can't* handle that speed.
Xilinx XAPP622 shows how it can be done:
Regards, Allan
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Maxim's MAX108 (8 bits, 1.5Gsps) has internal demux. It should not be very difficult to use a Xilinx Virtex-II /Pro device to interface with it. I think the FPGA device could run at 500MHz internally. But it
Howdy Ray,
How fast were your IOB's toggling on that design? Was it really
960 MHz? A coworker and I got to looking yesterday, and it appears that the general purpose IOB hasn't really gained any clock rate performance since VirtexE - all the way to now with the Virtex4. We were hoping to do 1.25 GHz LVDS (or any other standard), but our FAE is steering us away from doing anything much over 840 or 900 MHz. Comments from Xilinx reps also welcome...BTW, Alex, I agree with Ray. 500 MHz LVDS should be doable without alot of grief. Just be aware that the internal termination can be less than ideal.
Have fun,
Marc
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Symon wrote: >>Just be aware that the internal termination can be >>less than ideal. >
Howdy Symon,
We are using the internal _DT resistors on a V2P7 for receiving a LVDS clock that is slightly over 600 MHz, as well as the source synchronous data that goes along with it. It technically works (we never have bit errors over all operating conditions), but using a differential probe at the vias immediately below the inputs pins show that there isn't much margin - the signal quality looks pretty poor.
A more serious problem that we had was with a 600+ MHz GCLK input. What we believe we discovered was that a nearby GCLK input with a single ended 3.3V 66 MHz clock was affecting its signal quality enough that we'd sometimes miss clocks. The 66 MHz clock looked good (no excessive overshoot or other noise on it). Lowering the frequency to 311 MHz, with no change to routing, fixed the problem.
Have fun,
Marc
fitting
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