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Interface Bidir IO datalines to dualport RAM within FPGA - URGENT

====== URGENT ======

I have a small query and if possible do help me on this issue.

| |FPGA |========= | -->| Din Processor| | This is my dual port memory data line |

Reply to
karthik
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I'm assuming a synthesis tool cannot work with the 'process' block as you have it coded. Otherwise, you may find support in comp.lang.vhdl forum.

You should describe the registered input path as one process, the registered output path as another, and the tristate as a continous assignment.

-- Registered Input path process(ebmclk) begin if (ebmclk'event and ebmclk='1') then datain HAPPENS

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/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
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Reply to
Paulo Dutra

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