Instantiating addsub, comparators in Xilinx

Hi, Please do the following way:

LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.all;

signal A : unsigned(4 downto 0); -- example signal B : unsigned(4 downto 0); -- example

In the code area,

-- they can be in process or between process area. A

It may be that the rest of your design precludes resource sharing. Every time I've needed an adder or subtractor, I write code similar to what Weng describes.

For example, the following code will create only one adder:

if (add) then result comparators as well?

Why instantiate?

-a

If you want to share an adder, it is best to describe exactly how in your code.

Resource sharing by synthesis requires duplicated descriptions or a selection that can be made either by muxing inputs or outputs, like this:

if op1 then q_v := A + B; else q_v := C + D; end if;

I might duplicate a register description by mistake and be happy about a silent band-aid from synthesis. Or I might prefer just a warning so I can clean up my code. Then again, I might duplicate a register just to buffer the signal and prefer that synthesis keeps hands off.

-- Mike Treseler

Hi, I was doing that before but I found that each + that I use generates a

32-bit adder under the synthesis report which increases the LUT usage by quite a fraction. After that I tried to multiplex them to a addsub component and the LUT usage went down from 90+% to 80+% (I'm using the old RC100 board with spartan II so I have limited resources :( ). I was wondering if there are any other components that I can instantiate for comparators as well?

Does resource sharing also apply for a + sign in different states? It appears the synthesizer doesn't like my code then.

Adders are cheap in FPGAs. Two adders will be instantiated because 1) A and Z are different targets and 2) two muxes on the inputs require two levels of logic - the same amount needed to implement two adders.

Usually the syntesis does a great job of optimizing where it makes sense. Using one adder for multiple results with a wide input mux will probably not benefit anyone.

If you feel that this resource sharing is critical to your design, you will have to manually implement the multiplexers and thereby increase the total resources needed in your design.

Are you optimizing for speed or area?

-a

There are no guarantees either way. But it doesn't really matter. There are not really any "adder" primitives inside the fpga. Only gates and flops.

All synthesis guarantees is a netlist that simulates the same as the source code. There is no guarantee that the RTL or technology schematic output will look like I expect. But it will work.

If I code for an input mux with one adder, I just might get two adders and an output mux, if that better matches the constraint settings or the whim of the synthesis algorithm. Or I might get just what I expect. Or I might get something completely different.

Luckily, synthesis does a better job, on the average, of packing gates into a arbitrary device than I do.

-- Mike Treseler