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Inputs as an Array in Verilog??

Hi Guys:

I am working on an application where I have a large number (264) inputs to a single Verilog module. Each input is an 8-bit number. I would like to be able to refer to these inputs as members of an array, with a subscript, for ease in handling them in the program.

The only way I can see is to set up an array register, then individually assign each and every input to a specific register in the array. This going to be a lot of typing and I'd have to constantly refresh the assignment in the program. Is there an easier way to do this? Can inputs be directly arrayed in Verilog...and, if so, how would they be referred to in an instatiation, etc? I'm working with a Xilinx Spartan-3 and ISE.

Thanks for any replies.

Don

Reply to
eromlignod
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Are you saying that they start life as an array of 264 reg[7:0]? Or are you saying that they start life as 264 differently-named reg[7:0] (or wire[7:0]) signals? If the latter, may I politely ask what the hell you are doing?

In "classic" Verilog you can't pass arrays of vectors through a port, so you must create a port that is 8*264 bits wide, and copy each of your 264 inputs to one 8-bit slice of the array. A generate loop will allow you to do that easily:

reg [7:0] massive_array_of_signals [0:263]; reg [0:8*264-1] flattened_array;

genvar i; generate for (i=0; i

Reply to
Jonathan Bromley

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