Input stage for VHF frequency counter in an FPGA?

The other day I found myself needing a short gate time ~200 mhz frequency counter for an automated test, and since I had an FPGA board on hand I whipped one up quickly. Getting it reading and reporting to my computer was the easy part.

Ah, the input stage....

I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p or a little more if it's high-Z. The output of the device under test has a transformer and then a series cap to create an unbalanced output.

I did something ugly with a 3.3v cmos 7406 varient and a feedback resistor, which works well enough to get an accurate reading on one version of the device under test, but not on the other (both have been verified with real test equipment) It also tends to self-oscillate with no input...

What would be the right way to do this using on hand parts, such as abused logic, little 1:1 or 2:1 RF transformers, etc? One idea is to use another gate with a feedback resistor and cap to ground in the hope of establishing the threshold level, and then using a transformer to swing another input above and below this. Most parts on hand are SMD - which means dead bug construction in SOIC scale under the maginifier - discourages extensive experimentation.

Why do most abuse-of-logic RF applications seem to use NAND gates rather than inverters? From a digital perspective NAND gates are a universal element, but once you tie their inputs together, is there something to be gained from having two inputs in parallel?

Is there a way to use a differential input configuration on an FPGA to input a balanced RF signal directly? Theoretically this should be an FPGA clock input... The device in use currently is an Altera Stratix II, but a Xilinx S3 kit is available.

If ordering things, what would be a good default low supply voltage HF/VHF gain component to have on hand? I seem to recall lots of last-millenium ham designs using the MC1350P video IF amp, but what would make sense today?

Reply to
cs_posting
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Does the FPGA have LVDS option inputs ? If it is new enough to have those, they are differential amplifiers, designed for current mode signals, and will work with thresholds

Reply to
Jim Granville

For gain, have a look at MMICs. Minicircuits sell them in kits that give you a good range of performance. They're easy to use, and run on a single supply.

I think the idea of using the LVDS inputs on the FPGA is a good one, if you can get that into the clock lines you need to use. Otherwise, you only need a little gain to get to levels you need for logic input. Do your clock input lines have a bit of hysterisis? Do they have high enough input impedance to be used with a step-up transformer? Can you reliably bias the transformer DC return to a point between the hysterisis trip-points. I suspect you can do a better job with your logic-gate amplifier, too. Or you could make a fancier input using one of the very fast comparators.

Cheers, Tom

Reply to
K7ITM

As Jim has said LVDS is a good way. Just watch the common mode input range. You can use a RF transformer to rebias the DC level to get arround any issues.

Another way is to use a single ended standard like SSTL and DC bias the input to the reference voltage used for the SSTL. You do need to have access to Vref pins on the Spartan-3 to use this technique.

We have support for LVDS and SSTL in our boards but I am not sure about the Spartan-3 starter kit.

John Adair Enterpoint Ltd. - Home of Raggedstone1. The low Cost Spartan-3 Development Board.

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Reply to
John Adair

7406 is open collector. Did you mean 7404?

What size feedback resistor? What sort of oscillations?

I've had reasonable luck with that sort of hacking. Not great.

What's the output of your gate look like? Is it cleanly switching or struggling to switch at that speed?

You might want to skip the external gate and use an inverter in the FPGA out to a feedback pin. That gets the feedback covering the input pin that you are really interested in.

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Reply to
Hal Murray

Beside that no frequency is mentioned, I'd have a look at line receivers.

Rene

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Reply to
Rene Tschaggelar

the only gain is some PWB layout simplifications and less wasted part sections.

I am thinking on the order of a single transistor amplifier to go to logic levels, then characterize it for delay issues.

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Joseph2k

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Reply to
Fred Bloggs

On a sunny day (22 Feb 2006 19:01:44 -0800) it happened cs snipped-for-privacy@hotmail.com wrote in :

Just a partial reply... I think 7400 series should stop way below 200mHz, perhaps 50MHz?

I would make a small diff amplifier, did something 40 years ago (yes 40!) with I think it was BFY90 transistors, then invert with 2 more and drive the LVDS input.

-------------------------------- +5 or + 12 | | | [ ] [ ] [ ] R4 | |------------ __|__ |-----|-------- | | | |/ \| | | |/>e < \|

---| NPN |---- | |----| |--- in |\> e | |----------- LVDS - | | | [ ] [ ] [ ] | | R5 | R6

---------------------------------------------- GND

R4 could be a current source too, set it so it is guaranteed that the voltage across R5 and R6 (max i in one leg) cannot exceed FPGA max in.

Gives you some input protection The 'bias voltages can be generated with diode drop. No time now to enter it in spice to get response..... You can use simple junction FETS for the first stage too.

There are also nice chips, but transistors I have always in the box.

Reply to
Jan Panteltje

It's either a 74AC04 or possibly a 74HC04 (it's upside down so I can't tell) and it's self oscillating at 294 mhz - (it's stable enough for the counter to read... a fast scope shows it approximately as a sinewave.

It seems to be oscillating at about 1/tpd... can't even really pull it much with finger capacitance - only about 10 mhz.

Interestingly, if I short a the floating input-output pair of an unused inverter with the scope probe, that runs a bit slower around 260 mhz... wheras the gate in use has about 20k of resistance in the feedback path.

I may give your transistor circuit a try, either with components or simulation, thanks.

Reply to
cs_posting

What about using a stand-alone LVDS receiver? Eg. Pericom PI90LV179W.

Reply to
Spehro Pefhany

I'm surprised any CMOS 7406 variant really goes to 200MHz! I think you got lucky with the one that did work.

I like high-speed comparators (often called "differential receivers" or "LVDS receivers" on the spec sheet) for this.

The nice thing about differential receivers are:

  1. Easy to set the comparison level.
  2. Lowish input impedance but not too low, such that you set the impedance by putting a 50 or 100 or whatever ohm resistor there.
  3. At least for the non-LVDS parts, there's only one or two receivers per package so even when it's not SMD it's easy to do dead-bug prototyping.
  4. They already have some semblance of defined open-circuit response (usually called "fail-safe" for some bizarre reason in the spec sheets) to prevent oscillating.

Usually the hex inverter packages cost a little bit more than the

4xNAND gate packages. It's nice to have the extra input to act as an enable etc. And once you start running these parts into the linear region you probably do not really trust using the other sections for other functions.

You can even feed in non-balanced RF subject to some limitations.

VHF? MMIC's, at least as long as you have only need for AC coupling.

Tim.

Reply to
Tim Shoppa

From: cs snipped-for-privacy@hotmail.com on Wed, Feb 22 2006 7:01 pm

If you want some good results, use a high-speed comparator device. The Maxim MAX9010 family of comparators is fast (5 nSec propagation delay) and it works into a TTL load.

At 1 V p-p you've got the input overdrive to insure fast rise and fall times of the output. Note: 200 MHz (if that is really what you wanted to write) has a period of 5 nSec so even this very fast comparator is going to be pushed for a good output. On the other hand it is STABLE and won't "go into oscillation with no input."

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Samples are available. One in the family is in a SOT23 package, the rest smaller.

The MC1350P is second-sourced by Lansdale. It is still a very good differential in/out building block with good AGC control. The MC1349P is a pin/function equivalent and can be ordered from Dieter Gentzow's PartsAndKits.com at 3 for $3. Same place is a good source of small-quantity toroidal cores. Both ICs are called out with 12 VDC supplies but they will work down to 9 VDC with little degredation. Open-collector outputs, constant 5 KOhm || 5 pFd input, AGC control down to 60 db (if needed).

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Reply to
LenAnderson

There are some newer low voltage CMOS gates that are much faster than AC series, I think they are called LVC and a few other names depending on the manufacturer. The really fast ones don't support 5V supply operation because they are made on a fine geometry process. This also makes them faster. It would be very hard to stop it from self oscillating with no input signal. In order to have a meaningful way of determining if you have satisfied this requirement for not self-oscillating, you would first have to define what is the minimum input amplitude that you expect it to be able to accept and produce an output with reasonable duty cycle etc. Another approach would be to make an input buffer that does self oscillate and make a separate detector that measures the input signal amplitude and disables the measurement when the input amplitude is below a certain threshold.

Chris

Chris

Reply to
Chris Jones

cs snipped-for-privacy@hotmail.com skrev:

snip

The FPGA already has a balanced input, lvds. have you tried that with a few resistors or maybe a RC filter on signal to set the treshold on one input and the signal on the other input? or maybe even a cap into a cmos input biased to close but not quite vcc/2

1Vpp should be plenty, think the thresholds for ldvs is max 100mv

-Lasse

Reply to
langwadt

That sounds like a good idea, because theoretically we actually have some on hand somewhere, I'll have to see if I can scare them up.

While connecting to the FPGA directly would be simpler, I do like the idea of using an external chip as a bit of a 'fuse'. (Though transformer coupling into the FPGA should reduce some risk)

Reply to
cs_posting

Second that. We've tested the Xilinx Spartan3 LVDS inputs and they are excellent, super-fast comparators.

John

Reply to
John Larkin

Found one and wired it up as the datasheet suggests - cap coupled input to half the differential pair, the other side floating at the reference output pin voltage with decoupling cap to ground, terminating resistor across the pair. Worked quite well.

The xilinx S3 kit from digilent doesn't seem to be designed with using the differential input capability as the pairs are split up all over the place. Not certain that I couldn't bias one input of a pair as a reference wherever it is and drive the other pin wherever that is, but putting it all in a little package seemed simpler.

Reply to
cs_posting

Be sure to check the output with a scope.

Years ago, I used a PECL=>TTL part. That was real/old, 5V TTL. The problem was that I really wanted a CMOS output and what I got was a TTL signal that only went up to 4V or so. We had to run it through an AC dead-bug to get what we wanted.

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Reply to
Hal Murray

Good point to keep in mind. In this case though it's all 3.3v families, and LVTTL seems to have nearly the same Vih/Vil spec as LVCMOS. The part is spec'd with minimum Voh of 2.4v.

Reply to
cs_posting

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