Before going into details I want to explain the background:
I am using an FPGA to deal with signals coming from an external USB transceiver.
This USB transceiver has an 16bit parallel interface. The data coming into the FPGA are synchronous to a clock which is generated by the USB transceiver.
I use that transceiver clock to feed my PLL (input frequency 30MHz).
Of course there is also the other direction that is I have to send data back to the USB transceiver. These data have to be synchronous to the transceiver clock.
Now I ask myself which clock to use correctly to generate data to send back to the USB transceiver.
When I use this input clock I would like to know what timing constraints I have to consider for the data I send back to the transceiver so that I do not violate Tsu, Th ... Or would it be more preferable to use a different clock (1:1) maybe coming out of the PLL ?
Any ideas are highly appreciated.
Rgds André