I've discovered that Synplify no longer requires the use of $readmemh / $re= admemb to initialize inferred blockRAMs or ROMs. I thought I'd post some e= xamples of this for my own future reference. You can now use the SystemVer= ilog-style array initialization. You can do this directly, or by using a m= ultimensional parameter set in a package file. (Don't forget to check the = 'SystemVerilog' option box in Synplify.) You can also initialize a RAM/ROM= using a function you define in a generate loop. (You have to use a genera= te loop because an 'initial' loop is ignored by Synplify.) You could use t= his, for example, to create a sine/cos lookup table. A few examples below.
/***************************************************************** * Inferred ROM Initialization Using SysVerilog Array Init *****************************************************************/ module rom0 (input clk, input [5:0] addr, output [9:0] dout); reg [7:0] rom [0:63] =3D '{ 1, 3, 5, 7, 9,11,13,15, // init values 0, 2, 4, 6, 8,10,12,14, 3, 6, 9,12,15,18,21,24, 1, 3, 5, 7, 9,11,13,15, 0, 2, 4, 6, 8,10,12,14, 3, 6, 9,12,15,18,21,24, 1, 3, 5, 7, 9,11,13,15, 0, 2, 4, 6, 8,10,12,14}; reg [7:0] raddr; always@(posedge clk) raddr