initializing arrays with Verilog and XST

XST may support the initial block: initial begin reg_array[0] = 4'h1; reg_array[1] = 4'h9; ... end

They *do* support initial assignment to simple registers: reg [3:0] RegArrA = 4'h1; reg [3:0] RegArrB = 4'h9;

John-

Thanks for the reply.

Yes single reg initialization works Ok. But I've not figured out yet how to init one or more that are part of an array declaration.

I recall that in the past XST has referred to a register bit as something like reg_array_0, and that could be used in the INIT attribute, but I don't know XST's method for specifying an array element, or a bit within an array element.

-Jeff

This may not be the correct method to do it; but why dont you look at the synthesized output (synthesizing is done with out including the INIT part) and find out the name of the registeres you want to initialise. And then use INIT in the code with that name. Try to use INIT in the ucf. Also you can use microsoft excel to generate INIT strings if the array is large. regards Sumesh V S

Sumesh-

Thanks very much Sumesh, that was a good idea. I located the registers in the RTL schematic, and I found that I can do:

reg [3:0] reg_array [3:0];

// synthesis attribute INIT of reg_array is 8'h17

which I'm hoping will initialize the first 2 registers in the array. But this:

// synthesis attribute INIT of reg_array_0_0 is 1'b1

still gets the XST "ignored" message (I was hoping it might initialize the first bit in the first register).

Questions for anyone:

1) Does XST allocate an array of registers starting with least-significant index?

2) Is there some Xilinx documentation on this that I'm just not finding? App notes? Something else?

-Jeff