initializing a small array in Verilog

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In my Verilog code I have this line:

   reg [1:0] ip_list [0:3] = { 2'd2, 2'd1, 2'd0, 2'd1 };

Both Icarus and Vivado seem happy with it and it does what I expect.

However, I recently discovered Verilator and its lint capability so I've
been running it over all my code to see if there is anything I ought to
clean up.  Verilator does not like this code, it says the LHS only has 2
bits while the right is 8 bits, so I'm wondering if I should be writing
it differently.  Maybe I've only been lucky so far that it's worked at
all and I'd rather have my code correct than lucky.

Thanks for any help,
Dave

Re: initializing a small array in Verilog
On Saturday, January 12, 2019 at 3:34:25 PM UTC-7, David Bridgham wrote:
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That does not look like it should work.  If you set the tool to SystemVeriliog mode you should be able to initialize the reg like this:

   reg [1:0] ip_list [0:3] = '{ 2'd2, 2'd1, 2'd0, 2'd1 };  // note extra tick

In Verilog-2005 mode, I think you should only be able to set the unpacked elements individually or with $readmemh.

Re: initializing a small array in Verilog
On 1/13/19 12:28 PM, Kevin Neilson wrote:

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Neither $readmemh nor setting the entries individually are particularly
appealing so I guess it's time to learn about SystemVerilog.

And, in fact, I've been reading up on it since seeing your response.
Enums and structs, I should have looked into this before.  I could like
this language.

So that extra single quote you added, what are the semantics of that?  I
see it often enough in examples when I'm reading about SystemVerilog but
I have yet to find anything that describes what it actually means.

Thanks,
Dave


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