Initialize RAM in IGLOO

Hi all.

I am making a design for an IGLOO FPGA from Actel and I have have added a Two Port RAM component in Libero (the development tool). Here I can choose to "Customize RAM Content" and have imported an Intel Hex File.

This works perfectly in simulation, but not post-synthesis and layout simulation.

Can anyone help me with how I can make this part of the RAM (from address 0 and forward) initialized with the content of my Intel Hex File even after synthesis?

If the program does not support this, has anyone experience on how to do/code this in VHDL?

The Intel Hex File is generated from a compiler, so I have to read the file in as my compiled design evolves. I can not just hard code it once and for all.

Best Regards Rgr

Reply to
Rgr
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IGLOO does NOT support RAM initialization

the init is only provided for simulation, the FPGA itself can not have inited rams

Antti

Reply to
Antti

SRAM blocks in PA3/Fusion/Igloo are initialized via the UJTAG interface or from the design logic. You might find this helpful:

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Although I've never tried, it may be possible to use the Igloo's FlashROM (along with a bit of design logic) to initialize the RAM (although, this may or may not be enough data for what you want to initialize).

regards, Kris

Reply to
Kris Vorwerk

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r

NONO, there is no JTAG access to the RAM (like it is available in xilinx)

there is possibility to ADD USER LOGIC connected to UJTAG that will allow the rams to be loaded, but it also needs external JTAG tap master to actually load the init data

the flashROM is way too small, so not an option at all.

so whatever you do, you need USER logic to WRITE tot he RAM so there is no real init possible, means user logic writes AFTER the FPGA comes alive, the RAMs are not initialized during power up

Antti

Reply to
Antti

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