Hi all.
I am making a design for an IGLOO FPGA from Actel and I have have added a Two Port RAM component in Libero (the development tool). Here I can choose to "Customize RAM Content" and have imported an Intel Hex File.
This works perfectly in simulation, but not post-synthesis and layout simulation.
Can anyone help me with how I can make this part of the RAM (from address 0 and forward) initialized with the content of my Intel Hex File even after synthesis?
If the program does not support this, has anyone experience on how to do/code this in VHDL?
The Intel Hex File is generated from a compiler, so I have to read the file in as my compiled design evolves. I can not just hard code it once and for all.
Best Regards Rgr