Initialization of arrays in Verilog

Hi!

Can anybody give me a hint on how to initialize an array of registers in Verilog with Xilinx ISE 7.1i? I tried the following code:

| reg [9:0] palette [3:0]; | // synthesis attribute INIT of palette is "40'b0000000011000000001101111101111101111000"

XST accepts the code (== does not generate error messages or warnings), but seems to discard it later (currently I only read from the array, but later there will be write access, too):

| WARNING:Xst:653 - Signal is used but never assigned. | Tied to value 0000000000.

Since all read accesses will result in '0' the registers are optimized away later by XST.

I started my project with ISE 8 which supports Verilog "initial" blocks. Using those the following works well:

| initial begin | palette[0] = 10'b0000000011; | palette[1] = 10'b0001110101; | palette[2] = 10'b0111110111; | palette[3] = 10'b1101111000; | end

But now I have to synthesize the design using ISE 7.1i...

Thanks! Till.

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real e-mail: wollenberg (at) web (dot) de
Reply to
Till Wollenberg
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Till Wollenberg wrote: ...

Tell us why you have to synthesize with 7.1i

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
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Reply to
Uwe Bonnes

Hi!

  • "Uwe B> ...

Updating to 8.1i would surely solve my problem but I don't have appropriate permissions and so I'm stuck with 7.1i at least for the next days.

I thought that there *must* be a way to initialize arrays with

7.1i. Googling a bit I found some discussion threads exactly covering my problem but they all end up without a solution.

Till.

--
real e-mail: wollenberg (at) web (dot) de
Reply to
Till Wollenberg

You could probably instantiate distributed RAM primitives and then defining the contents of the ram through defparam.

See for example

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Or find it in lib.pdf in your local Xilinx documentation directory.

The problem is that you don't have vendor neutral HDL code any longer...

/Andreas

Reply to
Andreas Ehliar

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