Hi!
Can anybody give me a hint on how to initialize an array of registers in Verilog with Xilinx ISE 7.1i? I tried the following code:
| reg [9:0] palette [3:0]; | // synthesis attribute INIT of palette is "40'b0000000011000000001101111101111101111000"
XST accepts the code (== does not generate error messages or warnings), but seems to discard it later (currently I only read from the array, but later there will be write access, too):
| WARNING:Xst:653 - Signal is used but never assigned. | Tied to value 0000000000.
Since all read accesses will result in '0' the registers are optimized away later by XST.
I started my project with ISE 8 which supports Verilog "initial" blocks. Using those the following works well:
| initial begin | palette[0] = 10'b0000000011; | palette[1] = 10'b0001110101; | palette[2] = 10'b0111110111; | palette[3] = 10'b1101111000; | end
But now I have to synthesize the design using ISE 7.1i...
Thanks! Till.