Initialization of arrays

How does one initialize 'nibbles' in verilog the same way as 'longreg' is initialised .. ?

reg [1023:0] longreg =

576'h555555555555555D00014AB7AE08002143658709800054; reg [3:0] nibbles[0:256];

(Enviroment is Xilinx/Linux ISE xst)

I would prefer a vendor neutral way.... but if it's not possible tweaks are ok :)

Reply to
posedge52
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Have you tried?

reg [3:0] nibbles[0:256]; initial begin nibbles[0] = ; nibbles[1] = ; ... end

Reply to
root

I have seen that in some other post. The catch is that it will require reformatting of input data and becomes messy with frequent copy & paste from binary->text generator into source code. So I look for something where I can simply paste a hexstring right into code as a initialisation string. It doesn't make sense that it's alright for 1 bit wide arrays. But not for an 'n' wide array.

Reply to
posedge52

That's a limitation/idiosyncracy of Verilog. What you call a "1-bit wide array" isn't really an array at all -- it's a sized-vector. In Verilog, 2-D arrays are 'unpacked' arrays, what have all sorts of painful baggage (as you've found out.)

Verilog-2001 allows multi-dimensional packed-arrays, but they won't help you out here.

reg [3:0] useless_packed_array [0:39][0:15]; // Verilog-2001 integer i [3:0];

Systemverilog adds multi-dimensional UNpacked-arrays, which VHDL has already supported since the dawn of time. Of course, Xilinx XST will need to catch up and start supporting Systemverilog. (Altera Quartus

7.2 is already there!)

logic [7:0][3:0] unpacked_array; // Systemverilog logic [7:0][3:0] unpacked_array2; // Systemverilog initial unpacked_array = { 8'd1, 8'd2, 8'd3, 8'd4 }; initial unpacked_array2 = { default: '0 }; // all 0 integer [3:0] i;

^^^Ok I didn't check that in Modelsim -- someone will correct me if that's wrong!

Reply to
rsl

Yeah, a little bit wrong.

By putting both subscripts on the LEFT of the declaration

logic [7:0] [3:0] something;

you are declaring a PACKED two-dimensional array - OK, and useful, but not what I suspect you mean.

Also, I don't think you can declare a packed array of any predefined integral type, so "integer [3:0] i" is illegal.

This looks closer:

logic [7:0] four_bytes [3:0]; // unpacked array of bytes integer i[3:0]; // unpacked array of integers

And then your assignment-pattern syntax is slightly wrong too:

No, you need the assignment pattern syntax with an apostrophe in front of the opening brace:

initial unpacked_array2 = '{ default: '0 };

Simple braces {} enclose a concatenation, which is just a way of writing a vector of bits and is largely unchanged from standard Verilog. Assignment pattern '{} "learns" its data type from the context, and can therefore be more intelligent than concatenation about which part of its contents goes into which part of the target. For example:

logic [7:0] [1:0] packed_two_bytes;

That declares a 16-bit vector that can also be thought of as two 8-bit vectors stuck together. Now....

packed_two_bytes = {8'hFF, 4'b1}; // concatenation packed_two_bytes = '{8'hFF, 4'b1}; // assignment pattern

Oops!!! The first assignment (concatenation) creates the value 12'b1111_1111_0001 (the concatenation of

8'hFF and 4'b1) and then assigns that to the 16-bit vector, so we get

packed_two_bytes[1] = 8'h0F packed_two_bytes[0] = 8'hF1

Betcha that's not what you wanted! The second (assignment pattern) form knows about the array-of-bytes data type of "packed_two_bytes" and will assign 8'hFF to packed_two_bytes[1], and 4'b1 to packed_two_bytes[0].

"default:" syntax is valid in assignment patterns, but not in concatenations.

Yes, it's confusing :-)

And yes, it's a pity that ISE isn't adopting SystemVerilog a little more briskly. SV provides structured data for designers, in the same way that VHDL users have had multi- dimensional arrays, records and suchlike since forever (as you correctly say). It also provides a few other useful goodies like "unique case", and some more radical enhancements such as interfaces. All these things are (a) useful, (b) important for well-structured RTL design, (c) relatively easy for synthesis vendors to implement. Don't let your synth vendor leave you stuck in the mediaeval rut of traditional Verilog - put pressure on them to implement SV design constructs sooner rather than later!

--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Jonathan Bromley

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