All-
I recently opened a case with Xilinx about initializing arrays of registers (search for thread "initializing array of registers in XST" in this group
The answer is coming back that XST 8.1 processes initial block constructs for registers, FSMs, and memories for synthesis, not just simulation.
Is that correct? Can anyone confirm that XST 8.1 actually changes the config bitstream based on initial block content, not just for simulation output files?
-Jeff
I can confirm that I saw this behavior producing accurate results though the syntheis constructs ended up non-ideal. More than 6 months ago I was using the reg declaration to initialize SRLs with non-zero data (reg [15:] MySRL = 16'h0802;) and found the INITs made it to the chip. Problem was, everywhere there was a one, the shift register split into pieces with the ones implemented as registers and the zeros implemented in SRLs as appropriate even though one SRL could have made the whole thing work.
I can't confirm that *everything* happens in 8.1.03i but it does more than Synplify's been doing with respect to initials.
- John_H
John-
Ok... but was this declaration actually inside an "initial begin" block or outside in some vanilla Verilog? I've tried the syntax above on single register declarations and it works, but I've had no luck on array of registers. I tried this syntax:
reg [31:0] array [11:0] = 64'h0C0001820C000080;
to set the first 2 regs in the array, but I ended up with no bits set.
This happened just because of the INIT synthesis attribute? Or XST wanted to do it anyway, regardless of initial values?
-Jeff
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