[info] Sine generation

Hello,

my experiment has shown that high-quality sine wave can be easily generated using linear interpolation. A simple look-up table and a small multiplier is necessary, however I use two LUTs instead of one, because this reduces complexity of the circuit. But for a specialized IC the one LUT-based approach should be considerably cheaper. The idea is as follows: the first LUT contains 256 unsigned 18-bit sine values in the interval of [0,pi/2), sampled uniformly. The second LUT contains differences between consecutive samples (as I said above, this can be computed on-line, but is not well-suited for an FPGA chip because of long latency compensation paths, i.e. many wasted LEs). This ROM has only 11 bits, because max{(sin(2*pi*(k+1)/256) - sin(2*pi*k/256))*2^18} is just 1609. An 18-bits wide phase word is composed of three parts: quadrant_indicator (the upper 2 bits), lut_index (the next 8 bits) and phase_residue (remaining 8 bits). This provides:

my_sin(x) = sign * lut_val[lut_index] + lut_dif[lut_index] * phase_residue;

Of course sign, lut_index and phase_residue depend on currently selected quadrant, but this just a trivial remark.

This simple scheme provides sine wave with 17 bits of accuracy, which can be used directly to feed a quadrature mixer. Another important property is that the interpolation error near pi/2 is negative (i.e. forall x . |my_sin(x)| < 1), so there is no need for guard bits. I have some ideas how to further increase accuracy, but I am not sure whether I should start developing them, because

17 bits are far better than any modern digital RF front-end expects.

I have implemented a complete quadrature mixer (not just an NCO) on a multiplierless Cyclone 1C6 and it occupies only 815 LEs, where the majority of them is consumed by a 17x16 shared multiplier. Its top performance is limited by M4K RAMs and for -6, -7 and -8 speed grades this is, respectively, 255.9 MHz, 226.3 MHz and 197.0 MHz.

So, this low cost and low complexity method needs 256 times smaller number of ROM cells than classical ROM-based designs and much less LEs than CORDIC-based approaches. Moreover, this is achieved without signal quality nor performance degradation.

Best regards Piotr Wyderski

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Piotr Wyderski
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"Piotr Wyderski":

another option might be to simply rotate a point XY by an angle alpha:

x(t+1) = x(t)*k1 + y(t)*k2 // k1 = cos alpha y(t+1) = -x(t)*k2 + y(t)*k1 // k2 = sin alpha

k1 and k2 might (depending on alpha) have 50% bits set, on average. So if alpha is fixed, and if n is the number of bits in x and y, one complete step is made by 2*n ADDs.

An average summand may be x or y shifted right by floor(n/2). The useful calc-precision below LSB(x) or LSB(y) is ceil(lg(n)).

So we'd need 2*n*(floor(n/2) + ceil(lg(n))) 1-Bit full-adders:

n : 1-bit-fulladders (average)

24: 816 23: 736 22: 704 21: 630 19: 532 18: 504 16: 416 14: 308 12: 240 11: 198 10: 180 8: 128

This method of course has the disadvantage of relying on a fixed alpha per step, and maybe a "zero-phase-counter" (to reset x and y, when t is a multiple of period) is needed.

Gruss

Jan Bruns

Reply to
Jan Bruns

Hi Piotr, You'll get considerably better accuracy, or considerably smaller lookup tables, by using the Sunderland algorithm and/or the sine difference algorithm. Best, Syms.

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Symon

Thanks, I didn't know about them. The "sin(2*pi*x) - x" trick is particularly nice, I'll think about incorporating it into my quadrature mixer to increase accuracy beyond 17 bits (just to check the idea, there's no technical reason to do so). However, compared to

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it seems that my algorithm (which is very simple, so I doubt that I am the first inventor of it) is much better, because it needs only 2^8 16-bit ROM cells to produce 17-bit approximation of sin(x), where those algorithms need 2^8 9-bit cells to produce ~12 bits of accuracy. :-)

Best regards Piotr Wyderski

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Piotr Wyderski

"Piotr Wyderski" wrote in news:d2rbm3$160 $ snipped-for-privacy@news.dialog.net.pl:

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I wrote an article for Analog devices several years ago that discusses sine generation. It was implemented on a DSP, but the concepts are the same.

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You might be interested in our ADDS-21261/Cyclone DSP & FPGA Evaluation Kit. It is being sold by Arrow with a promo price of $199.

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Al Clark
Danville Signal Processing, Inc.
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Al Clark

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