Inferring F7 / F8 Mux in Xilinx

I'm posting this here for my own future reference.

If you infer a mux with fewer than 2**n inputs, Vivado won't infer the F7 or F8 muxes. Here is the trick to make sure you get the best synthesis.

Example, 5-input mux:

wire [7:0] mux_inputs[0:4]; // only 5 inputs wire [7:0] mux_out; wire [2:0] mux_sel;

always@(posedge clk) if (mux_sel

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Kevin Neilson
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Here's an addendum. The style above only works for a 7-input mux, not a 5-input. For less than 7 inputs, Vivado still omits the F7. Here's the Vivado kludge:

wire [7:0] mux_inputs[0:4]; // only 5 inputs wire [7:0] mux_out; wire [2:0] mux_sel; (*keep="true"*) wire [2:0] dummy_x[5:7];

assign dummy_x[5] = 3'bx; assign dummy_x[6] = 3'bx; assign dummy_x[7] = 3'bx;

always@(posedge clk) if (mux_sel

Reply to
Kevin Neilson

Nah, that doesn't always work either. This seems to work more consistently:

(*keep="true"*) wire [7:0] mux_inputs[0:7]; // only 5 inputs used wire [7:0] mux_out; wire [2:0] mux_sel;

// Assign unused mux inputs to 'bx so there are exactly 2^n inputs assign mux_inputs[5] = 'bx; assign mux_inputs[6] = 'bx; assign mux_inputs[7] = 'bx;

always@(posedge clk) mux_out

Reply to
Kevin Neilson

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