Hello folks.
I have implemented the entity bellow by instantciating a dual ported block RAM with different bus widths (RAMB16_S18_S36 - I am developing for Virtex II or Spartan 3). Whereas it is relatively simple to do it by instantiacing the component from Xilinx library, I wonder if there is a way to code the module so that Xst infers the block RAM. I tried in one or two ways but it used logic in slices instead of BRAM and it required a lot of logic for a 1kib RAM. Could somebody give a hint on this? I looked at Xilinx documentation and couldn't find an example for this particular problem.
entity gaintab is Port ( -- ports de acesso do processador i_ProcAddr : in std_logic_vector(9 downto 0); i_ProcDataIn : in std_logic_vector(15 downto 0); i_ProcWr : in std_logic; i_ProcEn : in std_logic; i_ProcClk : in std_logic; o_ProcDataOut : out std_logic_vector(15 downto 0); -- ports de acesso interno (fpga) i_FpgaAddr : in std_logic_vector(6 downto 0); i_FpgaClk : in std_logic; o_FpgaDataOut : out std_logic_vector(31 downto 0) ); end gaintab;
TIA.
Elder.