Finally I could map to RAMB16 on Xilinx Virtex and Synplify using the followig:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.math_real.all;
entity DualPortMemory is generic ( DEPTH : positive; WIDTH : positive ); port ( -- port a (read/write) clka : in std_logic; ena : in std_logic; wea : in std_logic; addra : in std_logic_vector(integer(ceil( log2(real(DEPTH))))-1 downto 0); dia : in std_logic_vector(WIDTH-1 downto 0); doa : out std_logic_vector(WIDTH-1 downto 0); -- port b (read/write) clkb : in std_logic; enb : in std_logic; web : in std_logic; addrb : in std_logic_vector(integer(ceil( log2(real(DEPTH))))-1 downto 0); dib : in std_logic_vector(WIDTH-1 downto 0); dob : out std_logic_vector(WIDTH-1 downto 0) ); end entity DualPortMemory;
architecture rtl of DualPortMemory is
type MEM_TYPE is array(0 to DEPTH-1) of std_logic_vector(WIDTH-1 downto 0); signal memory : MEM_TYPE;
attribute syn_ramstyle : string; attribute syn_ramstyle of memory : signal is "block_ram"; attribute syn_ramstyle of memory : signal is "no_rw_check";
begin
-------------------------------------- -- Port A (read/write) -------------------------------------- p_Port_A: process( clka ) begin if ( rising_edge(clka) ) then
if ( ena = '1' ) then if ( wea = '1' ) then memory( conv_integer(unsigned(addra)) )