infer block ram with mismatched port width

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
hi

i have a question on how to infer a block ram with mismatched ports.
as far as i found out with google and the xilinx manuals this is how
to infer block ram with matching ports in read first mode:

architecture syn of spi_memory_dp is
    type ram_type is array (63 downto 0) of std_logic_vector(15 downto
0);
    shared variable RAM : ram_type;
begin
        process (CLKA)
    begin
        if CLKA'event and CLKA = '1' then
            if WEA = '1' then
                RAM(conv_integer(ADDRA)) := DIA;
            end if;
                DOA <= RAM(conv_integer(ADDRA));
        end if;
    end process;

    process (CLKB)
    begin
        if CLKB'event and CLKB = '1' then
                       if WEB = '1' then
                RAM(conv_integer(ADDRB)) := DIB;
            end if;
                DOB <= RAM(conv_integer(ADDRB));
        end if;
    end process;
end syn;


could somebody help me out how to modify this so that the data width
on port A is 32 bits and on port B 8 bits.
sorry but i could not find an example for this or figure it out
myself.
also is my example state of the art or should i change something?

thanks
urban.

Re: infer block ram with mismatched port width
Quoted text here. Click to load it

I don't believe port width mismatches can be inferred yet through any
synthesis tool.  I asked about the capability a few years ago with the
Synplicity synthesis products and found the support was not present
and not planned.

If you want native port mismatches, you'll probably have to
instantiate your memory blocks.

- John_H

Re: infer block ram with mismatched port width
Quoted text here. Click to load it
<snip>
Quoted text here. Click to load it

1. Infer 4 dual memories that are each 8 bits wide (i.e. the width of
the smaller port, in this case the 'B' side).
2. Use the lower two bits of the B side address gated with the 'B'
side write enable to generate 4 individual write enables for the above
mentioned 4 dual port memories.
3. The 'A' side write enable goes to each of the four dual port
memories.
4. During a 'B' side read, read from all 4 memories in parallel and
then again using the lower 2 'B' side address bits, mux the
appropriate byte to the 'B' side data out port.

There are other ways of doing this but the above is fairly forward to
follow.

The key ideas here are:
- If you want to use FPGA internal memory and it doesn't happen to
support mismatched data widths, then you have to instantiate multiple
smaller memories that have a data width that matches your smaller data
width.
- Wrap logic around those multiple memories to give the whole thing
the appearance of implementing dual port with mismatched data width
sizes.
Kevin Jennings

Site Timeline