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Incremental compilation problem

Hi all,

I am experimenting incremental compilation following the Quartus II software handbook. But somehow the fitter ignores the logiclock region assignments so it will redo the placement and routing everytime. Here is the related message:

--
Info: Detected 34 design partitions (excluding Top) using post-fit
netlists and LogicLock region assignments -- ignoring LogicLock region
assignments
Reply to
Hua
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Hi Hua,

The info message indicates that Incremental Compilation is indeed active and that placement is being preserved for the 34 partitions. All the message is saying is that you have at least one LogicLock region set to Autosize and/or Floating, but because you are asking Quartus to preserve a previous placement, the LogicLock assignment is being ignored. To avoid seeing this message, you should use the "Set Size and Origin to Previous Fitter Results" command on the LogicLock regions window right-click menu to remove the Autosize and/or Floating properties.

For more information on Quartus Incremental Compilation, I recommend you check out the Incremental Compilation Resource Center at:

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Thanks!

Gabriel

Reply to
gquan

Hi Gabriel,

Thank you for your reply. Yeah, all my logiclock region were set to autosize and floating. I have changed the setting as you suggested and the message was gone.

Now, I set the logic regions to preserve both "placement and routing". And my compilation time reduced to about 1 hour and 7 munites, comparing to the compilation time of 1 hour and 20 minutes before I use incremental compilation. Does this sound right to you? I was expecting more time deduction.

I have 34 logiclock regions in the design, but I didn't assign the top level to a logiclock region. Could this be the problem?

The messages below seem to suggest that the placement and routing was preserved.

Info: The Fitter has identified 35 logical partitions of which 34 have a previous placement to use Info: Previous placement does not exist for 5155 of 5155 atoms in partition Top Info: Previous placement and routing used for 5041 of 5041 atoms in partition xxxx:xxxx_1 Info: Previous placement and routing used for 5036 of 5036 atoms in partition xxxx:xxxx_2 ...................

But still, the log shows that the fitter spent 10 minutes on physical synthesis optimization for speed, so the placement took about 13 minutes. Then the router took about 36 minutes.

The top level only has some glue logic, most of the design are in the

34 logic partitions. If the placement and routing of those partitions are indeed preserved, it shouldn't take this long to route the top level.

Any comments?

Hua

Reply to
Hua

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