Hi all,
I am experimenting incremental compilation on a design. But the logiclock region assignments are ignored and it doesn't seem to save the compilation time on the second compile.
In the first compile I set the netlist type of design partitions to post-sysnthesis, then when it's done I changed it to post-fit and start the second compilation. I wonder which one of the following could be the reason? Or it's something else?
- I set the logiclock region size as auto and the origin as floating.
- I used maximum routing and physical thesize effort for timing. Are there any settings that may force the compiler recompile anything?
- Setting the netlist type to post-fit and set the fitter preservation level to placement will only take effect on the third compilation and later? The second compilation do not preserve anything because the first compilation did not got the information it needs for preservation....
Thanks in advance Hua