incremental chip building in ISE

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I am currently involved in a large FPGA project using Xilinx Virtex 2
pro devices. Building the FPGA from RTL can take quite a long time and
therefore, I was looking through the process to build the FPGA
incrementally. I am wondering if anyone has done this using the ISE 8.1
and if you know of a reference that explains this process clearly.

Thank you,


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