increase in delay when a port was removed from design (Xilinx Project Navigator 5.2i)

I am a beginner in VHDL using Xilinx Project Navigator 5.2i to design a 8-bit by 8-bit binary array divider, the maximum pad to pad delay that the 'Text-based Post Place & Route Timing Report' showed for the program below was found to be 77.233 ns (from m to r8 and from m to r8), but when the output port 'f' was removed from the design, the maximum pad to pad delay increased to 85.713 ns (from m to r8). The only reference to 'f' in the architecture is in line number 29 as "f