increase in delay when a port was removed from design (Xilinx Project Navigator 5.2i)

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I am a beginner in VHDL using Xilinx Project Navigator 5.2i to design
a 8-bit by 8-bit binary array divider, the maximum pad to pad delay
that the 'Text-based Post Place & Route Timing Report' showed for the
program below was found to be 77.233 ns (from m<1> to r8<0> and from
m<2> to r8<0>), but when the output port 'f' was removed from the
design, the maximum pad to pad delay increased to 85.713 ns (from m<0>
to r8<4>). The only reference to 'f' in the architecture is in line
number 29 as
 "f <= r2(8) or r3(8) or r4(8) or r5(8) or r6(8) or r7(8) or r8(8);"
I was wondering how this increase in delay happened when a port was
Also, the maximum combinational delay estimate in the synthesis report
is and 130.499 ns from m<0> to q<0> (without the port 'f') and 130.598
ns from m<0> to f (with the port 'f').
The device family is Spartan2 and device is xc2s15, package is cs144,
speed grade is -6 and design flow is XST VHDL.

VHDL Program:

entity div16x82 is
port (d:in bit_vector(7 downto 0);
      m:in bit_vector(7 downto 0);
      q:out bit_vector(7 downto 0);
      r8:inout bit_vector(8 downto 0);
        f: out bit);
end div16x82;

entity d5 is
port(di,mi,bi,ci:in bit;
       bo,ro:out bit);
end d5;

architecture arch5 of d5 is
bo<=((not di)and mi)or((not di) and bi)or(mi and bi);
ro<=di xor((not ci)and(mi xor bi));
end arch5;

architecture X of div16x82 is
component d5
port(di,mi,bi,ci:in bit;
     bo,ro:out bit);
end component;
signal r1,r2,r3,r4,r5,r6,r7,b1,b2,b3,b4,b5,b6,b7,b8:bit_vector(8
downto 0);
signal c:bit_vector(8 downto 0);

f <= r2(8) or r3(8) or r4(8) or r5(8) or r6(8) or r7(8) or r8(8);

d10:d5 port map(d(7),m(0),'0',c(1),b1(0),r1(0));
d11:d5 port map('0',m(1),b1(0),c(1),b1(1),r1(1));
d12:d5 port map('0',m(2),b1(1),c(1),b1(2),r1(2));
d13:d5 port map('0',m(3),b1(2),c(1),b1(3),r1(3));
d14:d5 port map('0',m(4),b1(3),c(1),b1(4),r1(4));
d15:d5 port map('0',m(5),b1(4),c(1),b1(5),r1(5));
d16:d5 port map('0',m(6),b1(5),c(1),b1(6),r1(6));
d17:d5 port map('0',m(7),b1(6),c(1),b1(7),r1(7));
q(7)<= not b1(7);
d20:d5 port map(d(6),m(0),'0',c(2),b2(0),r2(0));
d21:d5 port map(r1(0),m(1),b2(0),c(2),b2(1),r2(1));
d22:d5 port map(r1(1),m(2),b2(1),c(2),b2(2),r2(2));
d23:d5 port map(r1(2),m(3),b2(2),c(2),b2(3),r2(3));
d24:d5 port map(r1(3),m(4),b2(3),c(2),b2(4),r2(4));
d25:d5 port map(r1(4),m(5),b2(4),c(2),b2(5),r2(5));
d26:d5 port map(r1(5),m(6),b2(5),c(2),b2(6),r2(6));
d27:d5 port map(r1(6),m(7),b2(6),c(2),b2(7),r2(7));
d28:d5 port map(r1(7),'0',b2(7),c(2),b2(8),r2(8));
q(6)<= not b2(8);
d30:d5 port map(d(5),m(0),'0',c(3),b3(0),r3(0));
d31:d5 port map(r2(0),m(1),b3(0),c(3),b3(1),r3(1));
d32:d5 port map(r2(1),m(2),b3(1),c(3),b3(2),r3(2));
d33:d5 port map(r2(2),m(3),b3(2),c(3),b3(3),r3(3));
d34:d5 port map(r2(3),m(4),b3(3),c(3),b3(4),r3(4));
d35:d5 port map(r2(4),m(5),b3(4),c(3),b3(5),r3(5));
d36:d5 port map(r2(5),m(6),b3(5),c(3),b3(6),r3(6));
d37:d5 port map(r2(6),m(7),b3(6),c(3),b3(7),r3(7));
d38:d5 port map(r2(7),'0',b3(7),c(3),b3(8),r3(8));
q(5)<= not b3(8);
d40:d5 port map(d(4),m(0),'0',c(4),b4(0),r4(0));
d41:d5 port map(r3(0),m(1),b4(0),c(4),b4(1),r4(1));
d42:d5 port map(r3(1),m(2),b4(1),c(4),b4(2),r4(2));
d43:d5 port map(r3(2),m(3),b4(2),c(4),b4(3),r4(3));
d44:d5 port map(r3(3),m(4),b4(3),c(4),b4(4),r4(4));
d45:d5 port map(r3(4),m(5),b4(4),c(4),b4(5),r4(5));
d46:d5 port map(r3(5),m(6),b4(5),c(4),b4(6),r4(6));
d47:d5 port map(r3(6),m(7),b4(6),c(4),b4(7),r4(7));
d48:d5 port map(r3(7),'0',b4(7),c(4),b4(8),r4(8));
q(4)<= not b4(8);
d50:d5 port map(d(3),m(0),'0',c(5),b5(0),r5(0));
d51:d5 port map(r4(0),m(1),b5(0),c(5),b5(1),r5(1));
d52:d5 port map(r4(1),m(2),b5(1),c(5),b5(2),r5(2));
d53:d5 port map(r4(2),m(3),b5(2),c(5),b5(3),r5(3));
d54:d5 port map(r4(3),m(4),b5(3),c(5),b5(4),r5(4));
d55:d5 port map(r4(4),m(5),b5(4),c(5),b5(5),r5(5));
d56:d5 port map(r4(5),m(6),b5(5),c(5),b5(6),r5(6));
d57:d5 port map(r4(6),m(7),b5(6),c(5),b5(7),r5(7));
d58:d5 port map(r4(7),'0',b5(7),c(5),b5(8),r5(8));
q(3)<= not b5(8);
d60:d5 port map(d(2),m(0),'0',c(6),b6(0),r6(0));
d61:d5 port map(r5(0),m(1),b6(0),c(6),b6(1),r6(1));
d62:d5 port map(r5(1),m(2),b6(1),c(6),b6(2),r6(2));
d63:d5 port map(r5(2),m(3),b6(2),c(6),b6(3),r6(3));
d64:d5 port map(r5(3),m(4),b6(3),c(6),b6(4),r6(4));
d65:d5 port map(r5(4),m(5),b6(4),c(6),b6(5),r6(5));
d66:d5 port map(r5(5),m(6),b6(5),c(6),b6(6),r6(6));
d67:d5 port map(r5(6),m(7),b6(6),c(6),b6(7),r6(7));
d68:d5 port map(r5(7),'0',b6(7),c(6),b6(8),r6(8));
q(2)<= not b6(8);
d70:d5 port map(d(1),m(0),'0',c(7),b7(0),r7(0));
d71:d5 port map(r6(0),m(1),b7(0),c(7),b7(1),r7(1));
d72:d5 port map(r6(1),m(2),b7(1),c(7),b7(2),r7(2));
d73:d5 port map(r6(2),m(3),b7(2),c(7),b7(3),r7(3));
d74:d5 port map(r6(3),m(4),b7(3),c(7),b7(4),r7(4));
d75:d5 port map(r6(4),m(5),b7(4),c(7),b7(5),r7(5));
d76:d5 port map(r6(5),m(6),b7(5),c(7),b7(6),r7(6));
d77:d5 port map(r6(6),m(7),b7(6),c(7),b7(7),r7(7));
d78:d5 port map(r6(7),'0',b7(7),c(7),b7(8),r7(8));
q(1)<= not b7(8);
d80:d5 port map(d(0),m(0),'0',c(8),b8(0),r8(0));
d81:d5 port map(r7(0),m(1),b8(0),c(8),b8(1),r8(1));
d82:d5 port map(r7(1),m(2),b8(1),c(8),b8(2),r8(2));
d83:d5 port map(r7(2),m(3),b8(2),c(8),b8(3),r8(3));
d84:d5 port map(r7(3),m(4),b8(3),c(8),b8(4),r8(4));
d85:d5 port map(r7(4),m(5),b8(4),c(8),b8(5),r8(5));
d86:d5 port map(r7(5),m(6),b8(5),c(8),b8(6),r8(6));
d87:d5 port map(r7(6),m(7),b8(6),c(8),b8(7),r8(7));
d88:d5 port map(r7(7),'0',b8(7),c(8),b8(8),r8(8));
q(0)<= not b8(8);
end X;

Re: increase in delay when a port was removed from design (Xilinx Project Navigator 5.2i)
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Quoted text here. Click to load it

It's important to note that post place-and-route timing depends
heavily on the place and route.  That is, changes in the input design
that would seem to speed up the outcome may not due to the place
and route finding a better solution to the seemingly slower design.

The first place to look is in your timing constraints.  The place and
route engine usually stops to optimise as soon as the constraints are
met, thus not finding a potentially "optimum" placement / routing.
Also if you only constrain maximum pad-to-pad timing, removing the
path that originally had the longest delay would allow the tools to
take fewer optimization passes and thus probably not do as good a job
on the remainder of the design.

I doubt that removing port 'f' from your design caused the synthesis
to create more logic levels.  You can check this by looking at the
post-translate static timing rather than post place-and-route.


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