Does anyone possess an example of a core incorporated to the PLB of Virtex2Pro especially if the design is using FIFOs. I am trying to incorporate my DES core to the PLB bus of the Virtex2Pro for a Single PPC design.
Thanks, Noel
The "Create and Import Peripheral Wizard" is the place to start. It generates an example user pcore and the device drivers to interface to it.
FIFO, DMA, and interrupt support are all available.
Paul
el_boricua wrote:
I have read it but an example is more helpful to clear out the details of what is not in the document.
When you run the IP Import Wizard, it does generate a very nice example design. It was very helpful for me. Make sure you have the latest EDK service pack installed since Xilinx is continually adding features to this area of the tools.
Paul
el_boricua wrote:
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