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Incorporating CoreGen files in EDK 8.1 peripheral

Hi folks,

I have a problem and I need a clean solution: I created an OPB peipheral which includes AsyncFIFO (created with FIFO generator). I have included the edn (tried also with ngc) in bbd file and a VHDL wrapper (original, created by CoreGen). During build I get the following error: ERROR:NgdBuild:604 - logical block 'imam_0/imam_0/FIFO' with type 'async_fifo' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'async_fifo' is not supported in target 'virtex4'. I did managed to overcome the problem somehow several times by changing bbd and netlist filenames, but the problem comes to the surface every time I clean all the EDK project files.

Guru

Reply to
Guru
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The async_fifo.edn is generated on the fly through some HDL pragma calls that XST understands.

To integrate this into EDK flow, add OPTION RUN_NGCBUILD=TRUE into the MPD of your pcore. This allows platgen to integrate sub-netlist files into the generated NGC file produced by XST.

Guru wrote:

Reply to
Paulo Dutra

You may have already done this, but I thought to point it out anyway:

Make sure that the core netlist (edn, etcc) is in the directory like this

pcores/your_core_v_1_00a/netlist

And the bbd file should have lines like below: FILES your_netlist_names

HTH, Jim

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Guru wrote:

Reply to
Jim Wu

Hi Guru,

I solved that problem (when I experienced it) by adding the line OPTION STYLE = MIX to my mpd file.

/Johan

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Reply to
Johan Bernspång

Actually I have done all of that that what you suggested.

The problem is actually that during synthesis async_fifo.ngc is not copied to project/implementation/my_peripheral_0_wrapper directory. If I copy it manually the it works, otherwise not - weird behaviour. Maybe synthesis on the fly can help, since Xilinx peripherals are done that way (fifo in opb_ddr for instance).

Guru

Reply to
Guru

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