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"|->" implicate and sequence in SVA?

Hi all,

I have two problem of SystemVerilog Assertion. About property implication and sequence.

  1. Is //-------- property rule (a,b,c); @(posedge clk) a |-> b ##1 c; endproperty //--------

equal to //-------- sequence rule; @(posedge clk) (a&&b) ##1 c; endsequence //--------

  1. I was told implication can be same or next cycle. Is same cycle equal to "|->"? And is next cycle equal to "|=>"?

Thanks a lot!

Best regards, Davy

Reply to
Davy
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No. See the recent thread "implication operators in sva" on comp.lang.verilog. Also, you have parameterised the property but not the sequence.

Yes. See my post in the thread I just mentioned.

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Reply to
Jonathan Bromley

Hi Jonathan,

Thanks a lot! Now I understand what's "vacuous success" :)

Best regards, Davy

J>

Reply to
Davy

To myself.

##1 is equivalent to @ (posedge clk). So ##N is equvalent to repeat (N) @ (posedge clk) ?

Thanks! Davy

Davy wrote:

Reply to
Shenli

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