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Implementing control registers (VHDL)

Hello

I'm wondering how configurations registers are usually implemented. By this I mean I have in my design value I want to be run-time configurable. So each of this value is read (and read only), and on the other side, there is an address / data / strobe bus. So that a controller can read/write a register given it's adress.

I'm looking for a space efficent way. I don't think I can use memory blocks for this since they are all read in // ...

What I've come up with so far is

type reg_space is array (integer range ) of std_logic_vector(31 downto 0); signal registers : reg_space(63 downto 0); signal address : std_logic_vector(5 downto 0);

Then to write a value in a process :

registers(address)

Reply to
Sylvain Munaut
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You can't use a std_logic_vector as index - use an integer. If you need the address as output you have to convert it. Manfred

"Sylvain Munaut" schrieb im Newsbeitrag news:4108e760$0$31480$ snipped-for-privacy@news.skynet.be...

this I mean I have in my design value I want to be run-time configurable. So each of this value is read (and read only), and on the other side, there is an address / data / strobe bus. So that a controller can read/write a register given it's adress.

blocks for this since they are all read in // ...

0);

registers.

Reply to
Manfred Balik

I don't read need the address at output, it's read from fpga pins ( I know, here I put it as signal but it's a in port in my design ). How would I convert it to integer ? does that involves logic or it's just synctatic sugar ?

Sylvain

Manfred Balik wrote:

Reply to
Sylvain Munaut

If you look at the WISHBONE documentation I believe that they have an example of what you might be looking for (under SLAVE I/O ports)

formatting link

Good luck,

Edm> Hello

Reply to
Edmond Cote

Yes, VHDL is all about "syntactic sugar". VHDL uses strong typing which means you can only use a signal as its declared type, the tool will not "figure out" what you mean, you *must* tell it explicitly. If you want a tool that will make assumptions, you should be using Verilog.

To convert to an integer, you first must convert to a signed or unsigned type and then to an integer...

registers(TO_INTEGER(UNSIGNED(address)))

here I put it as signal but it's a in port in my design ).

synctatic sugar ?

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Rick "rickman" Collins

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Reply to
rickman

Yes, that's a lot of FFs.

Hopefully the numbers were just picked up randomly. I need something like 10 8 bits registers, for values that are continuously needed.

They other configurations options in my design are stored in dual port distributed ram.

Sylvain Munaut

Reply to
Sylvain Munaut

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