I am trying to use one of the enhanced PLLs in an Altera Stratix II (EP2S60F1020C4) on the Altera DSP Development board in order to synthesize from a 100 MHz input clock frequencies new clock frequencies in the range 20-150 MHz. The critical bit is: I need a frequency resolution of not more than 0.01 Hz, which is obviously not feasible with the built-in 9-bit PLL dividers.
I am therefore trying to build a so-called "two-modulus prescaler" PLL. In other words, I would like to use the FPGA's internal logic in order to build a frequency divider that toggles between division by N and division by N-1. By adjusting the duty cycle of the divider toggling signal, I should be able to achieve output frequencies corresponding to high-resolution factional frequency multiplication factors. The toggling frequency should obviously be well above the PLL's loop filter bandwidth. I believe I can achieve the required divisor resolution with
32-bit counters.Question:
- Has anyone here already done something similar and may be able to offer advice?
- I need to feed the fbin (feed-back input) pin of the PLL from the internal logic (i.e., the output of my Verilog-implemented two-modulus divider).
Is that possible at all in Stratix II without an external loop-back connection in hte PCB layout?
In other words, can the PLL feed-back input be driven by the internal logic, or are these only connected via a multiplexer to either the PLL phase detector or (exclusive or) the internal logic?
- If an external feed-back connection is necessary, is there any better or more elegant solution than using a jumper on one of the extension prototype connectors of the Stratix II EP2S60 DSP development board?
Any other suggestions for building such a high-resolution frequency synthesizer from a Stratix II are of course also welcome.
Thanks for any hints!
Markus