Implement a JTAG controller in an FPGA

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Anyone done a JTAG controller in VHDL or Verilog?

I want to use an FPGA to program another JTAG device.

Cheers,

Irish


Re: Implement a JTAG controller in an FPGA
As far as I remember, Lattice has a reference design on multiple
boundary scan port linker, see
http://www.latticesemi.com/products/devtools/ip/refdesigns/index.cfm

I think this can be used to program other devices through one
centralised device. Please correct me if I'm wrong.

Luc

wrote:

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Re: Implement a JTAG controller in an FPGA
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there are only JEDEC files for the those boundary scan linker designs, not
much useful at all

and I think OP was not looking for this type of thing but TAP master

Antti



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