Impact, SVF, assumed TCK frequency?

In the Xilinx SVF file, the assumed TCK is the maximum TCK frequency of the device. Look the datasheet of the FPGA or your CPLD (between 10 to

40 MHz).

Laurent

__________________________________ Q01 2004 -> Amontec will introduce a new USB JTAG POD based SVF ! ==================================

Hmmm. But when there's a chain of different devices, or even other brand names than Xilinx... I guess impact will use the lowest speed in the chain based upon the attribute in the BSDL files:

attribute TAP_SCAN_CLOCK of TCK : signal is (10.00e6,BOTH);

Is my assumption correct?

Petter

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The assumed frequency is 1MHz, this is documented in SVF app notes and the iMPACT user guide.

If you wish to get absolute time generated > In SVF files generated by impact there will be delay statements on the